TLP7930F Datasheet | Toshiba

Features (1) Output clock frequency: 10 MHz (typ.) (2) 16 bits resolution no missing codes [ENOB: 12 bits (typ.)] (3) Integral non-linearity: 4 LSB (typ.) (4) Input offset voltage: 1.4 m V (typ.) (5) Operating temperature range: -40 to 105  (6) mon-mode transient immunity: 15 k V/µs (min) (7) Safety standards UL-approved: UL1577, File No.E67349 c UL-approved: CSA ponent Acceptance Service No.5A File No.E67349 VDE-approved: EN60747-5-5, EN60065 or EN60950-1 (Note 1) Note 1: When a VDE approved type is needed, please designate the Option (D4). ©2016 Toshiba Corporation Start of mercial production 2016-01 2016-05-09 Rev.3.0 4. Packaging (Note) TLP7930 TLP7930(LF1,TP1) TLP7930,TLP7930F TLP7930(LF5,TP5) 11-10C4S 11-10C401S TLP7930F(LF4,TP4) 11-10C405S 11-10C402S 11-10C404S Note: Through-hole type: TLP7930, TLP7930F Lead forming option: (LF1), (LF4), (LF5) Taping option: (TP1), (TP4), (TP5) ©2016 Toshiba Corporation 2016-05-09 Rev.3.0 5. Pin Assignment TLP7930,TLP7930F 5.1. Pin Description Pin No. 1 2 3 4 5 6 7 8 Symbol Description VDD1 VIN+ VINGND1 GND2 MDAT MCLK VDD2 Input side supply voltage Positive input Negative input Input side ground Output side ground Modulator data output Modulator clock output Output side supply voltage 6. Internal Circuit (Note) Note: A 0.1-µF bypass capacitor must be connected between 1 and 4 pins and between 5 and 8 pins. 7. Principle of Operation 7.1. Mechanical Parameters Characteristics Creepage distances Clearance Internal isolation thickness 7.62-mm Pitch TLP7930 7.0 (min) 7.0 (min) 0.4 (min) 10.16-mm Pitch...