1. GENERAL DESCRIPTION
The TMPR4955/56F is a 64-bit RISC (Reduced Instruction Set Computer) microprocessor that is
a low-cost, low-power microprocessor developed for interactive consumer applications including
set-top terminals, LBP(Laser Beam Printer), and video games.
• True 64-bit microprocessor, with TX49/H core.
• Optimized 5-stage pipeline
• System Address/Data bus
TMPR4955 : 32-bit System Address/Data bus
TMPR4956 : 32-bit or 64-bit System Address/Data bus
• Floating-Point Operation
Single or double-precision floating-point unit ( IEEE Standard 754 exceptions )
• 36-bit physical address space and 64-bit virtual address space.
• On-chip 32-Kbyte Instruction Cache and 32-Kbyte Data Cache.
4-way set associative and Lock function support
• Low power consumption
3.3 /2.5V Dual power supply (I/O:3.3V,Internal:2.5V)
Reduced power mode (Doze/Halt)
• Instruction cache prefetching
• Memory management unit
contains 48-double entry JTLB, 2-entry Instruction TLB, and 4-entry Data TLB
• Software compatibility with all MIPS processors
MIPS I, II, and III Instruction Set Architecture (ISA)
• EJTAG (Enhanced JTAG) debug support
• Package :
TMPR4955 : 160-pin QFP
TMPR4956 : 208-pin QFP
• Maximum operating frequency