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TC35273 - MPEG-4 Audiovisual LSI

Description

System Reset Input (Low Active).

When the LSI is reset, the reset pin has to be low for more than 16 clock cycles.

When power on, the LSI has to be reset after PLL locked.

Features

  • www. DataSheet4U. com U TC35273 is an MPEG-4 audiovisual codec LSI which supports 3GPP 3G-324M video telephony system. MPEG-4 video codec with QCIF (176x144 pixel) at 15 frames/s, AMR (Adaptive Multi Rate) speech codec, and ITU-T H.223 are executed concurrently at around 70MHz clock rate. U Three signal processing units, an MPEG-4 video codec, a speech codec / audio decoder, and a multiplex / demultiplex unit, are integrated on a single chip. P-FBGA201-1515-0.80A5 U A 12-Mbit embedded DRAM i.

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Datasheet preview – TC35273

Datasheet Details

Part number TC35273
Manufacturer Toshiba Semiconductor
File Size 284.19 KB
Description MPEG-4 Audiovisual LSI
Datasheet download datasheet TC35273 Datasheet
Additional preview pages of the TC35273 datasheet.

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Full PDF Text Transcription

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Preliminary TOSHIBA MPEG-4 Audiovisual LSI MPEG-4 Audiovisual Codec LSI TC35273 TC35273 Tentative Technical Data Sheet MPEG-4 Audiovisual LSI Features www.DataSheet4U.com U TC35273 is an MPEG-4 audiovisual codec LSI which supports 3GPP 3G-324M video telephony system. MPEG-4 video codec with QCIF (176x144 pixel) at 15 frames/s, AMR (Adaptive Multi Rate) speech codec, and ITU-T H.223 are executed concurrently at around 70MHz clock rate. U Three signal processing units, an MPEG-4 video codec, a speech codec / audio decoder, and a multiplex / demultiplex unit, are integrated on a single chip. P-FBGA201-1515-0.80A5 U A 12-Mbit embedded DRAM is integrated as a shared memory for the three signal processing units.
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