Datasheet4U Logo Datasheet4U.com

TC74AC573FW - Octal D-Type Latch

Download the TC74AC573FW datasheet PDF. This datasheet also covers the TC74AC573F variant, as both devices belong to the same octal d-type latch family and are provided as variant models within a single manufacturer datasheet.

Key Features

  • High speed: tpd = 6.0 ns (typ. ) at VCC = 5 V.
  • Low power dissipation: ICC = 8 µA (max) at Ta = 25°C.
  • High noise immunity: VNIH = VNIL = 28% VCC (min).
  • Symmetrical output impedance: |IOH| = IOL = 24 mA (min) Capability of driving 50 Ω transmission lines.
  • Balanced propagation delays: tpLH ∼.
  • tpHL.
  • Wide operating voltage range: VCC (opr) = 2 to 5.5 V.
  • Pin and function compatible with 74F573 Note: xxxFW (JEDEC SOP) is not avail.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (TC74AC573F_ToshibaSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
TC74AC00F Quad 2-Input NAND Gate Toshiba
TC74AC00FT Quad 2-Input NAND Gate Toshiba
TC74AC00P Quad 2-Input NAND Gate Toshiba
TC74AC02FN Quad 2-Input NOR Gate Toshiba
TC74AC02FT Quad 2-Input NOR Gate Toshiba

Other Datasheets by Toshiba

Part Number Description
TC74AC573F Octal D-Type Latch
TC74AC573FT Octal D-Type Latch
TC74AC573P Octal D-Type Latch
TC74AC574F Octal D-Type Flip-Flop
TC74AC574FT Octal D-Type Flip-Flop

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
TC74AC573P/F/FW/FT TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74AC573P,TC74AC573F,TC74AC573FW,TC74AC573FT Octal D-Type Latch with 3-State Output The TC74AC573 is an advanced high speed CMOS OCTAL LATCH fabricated with silicon gate and double-layer metal wiring C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. These 8-bit D-type latches are controlled by a latch enable input (LE) and a output enable input ( OE ). When the OE input is high, the eight outputs are in a high impedance state. All inputs are equipped with protection circuits against static discharge or transient excess voltage. Features • High speed: tpd = 6.0 ns (typ.