TMP91CW28 Key Features
- Instruction set is upwardly assembly code patible with the TLCS-90 16-Mbyte linear address space Architecture based on g
- 16-Mbyte off-chip address space for code and data External bus interface with dynamic bus sizing for 8-bit and 16-bit da
- 6 banks of registers (15) 4-channel chip select/wait controller (16) 48 interrupt sources
- 9 CPU interrupts: Triggered by software interrupt instruction or upon the execution of an undefined instruction 21 inter
- Three HALT modes: Programmable IDLE2, IDLE1, STOP Clock gear: Changes the frequency of high-frequency clock within the r
