Description
The ASPEN device (TXC-05810B) is a revolutionary, RISC-based processor designed to support the requirements of next generation multi-service access systems.
Features
- 155 Mbit/s bidirectional throughput RISC-based hardware architecture Dual independent CellBus interfaces for increased bandwidth or redundancy UTOPIA Level 2P interface for cell and packet transport 64-bit synchronous SRAM port for data storage Utilizes ASPEN ATM AccessEDGE firmware for design and field upgrades Cell insertion/extraction through host interface Message-based interface for host-ASPEN communi.
TXC-05810B Datasheet
