TQ8101C - 622/155 Mb/s SONET/SDH MDFP

Datasheet Summary

Description

Figure 2 shows a block diagram of the TQ8101C multiplexer, demultiplexer, framer, and PLL clock synthesizer (MDFP).

The primary purpose of TQ8101C is to integrate the conversion of serial and parallel SONET/SDH data with bit alignment and clock synthesis in a single device.

Features

Byte-wide Multiplexing, Demultiplexing, Framing, and PLL (MDFP) in one device.
Choice of STS-12/STM-4 or STS-3/STM-1 transmission rates.
Configurable master or slave reference clock generation and PLL bypass for external clocking.
77.76 MHz or 19.44 MHz output for the multiplexer; 77.76 MHz or 19.44 MHz and 51.84 MHz output for the demultiplexer.
External RC loop filter.
Pass-through mode and three loopback modes for enhanced filed diagnosti.

TriQuint Semiconductor

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Datasheet Details

Part number	TQ8101C
Manufacturer	TriQuint Semiconductor
File Size	227.38 KB
Description	622/155 Mb/s SONET/SDH MDFP
Datasheet	TQ8101C Datasheet
Additional preview pages of the TQ8101C datasheet.

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T R I Q U I N T S E M I C O N D U C T O R, I N C . TQ8101C The TQ8101C is a SONET/SDH transceiver that integrates Multiplexing, Demultiplexing, SONET/SDH Framing, clock synthesis PLL (MDFP), and loopback functions in a single monolithic integrated circuit. Implementation with the TQ8101C requires only a simple external RC loop filter and standard TTL and ECL power supplies. For optimal performance, the TQ8101C MDFP is packaged in a 68-pin multilayer ceramic (MLC) surface-mount package with an integral CuW heat spreader. The TQ8101C provides an integrated solution for physical interfaces intended for use in STS-12/STM-4 (622.08-Mb/s) and STS-3/STM-1 (155.52-Mb/s) SONET/SDH systems. The TQ8101C meets ANSI, Bellcore, and ITU requirements for a SONET/ SDH device. With a 51.

Published: Apr 16, 2005 |