Datasheet4U Logo Datasheet4U.com

U74AHC1G74 - SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP

Description

The UTC U74AHC1G74 is a single positive-edge-triggered D-type flip-flop.

inputs.

Features

  • S.
  • Operation voltage range: 2 ~ 5.5V.
  • Max tPD of 7.3 ns at 5 V.
  • Low static power consumption; ICC=2μA (Max. ).
  • ±8mA output drive at 5 V.

📥 Download Datasheet

Datasheet preview – U74AHC1G74

📁 Similar Datasheet

  • U74AHC1G02 - 2-INPUT NOR GATE (Unisonic Technologies)
  • U74AHC1G04 - SINGLE INVERTER GATE (Unisonic Technologies)
  • U74AHC1G06 - INVERTER (Unisonic Technologies)
  • U74AHC1G07 - BUFFER (Unisonic Technologies)
  • U74AHC1G09 - 2-INPUT AND GATE (Unisonic Technologies)
  • U74AHC1G125 - SINGLE BUS BUFFER GATE (Unisonic Technologies)
  • U74AHC1G126 - SINGLE BUS BUFFER GATE (Unisonic Technologies)
  • U74AHC1G14 - SINGLE SCHMITT-TRIGGER INVERTER GATE (Unisonic Technologies)
  • U74AHC1G32 - SINGLE 2-INPUT POSITIVE-OR GATE (Unisonic Technologies)
  • U74AHC1G34 - SINGLE NON-INVERTING GATE (Unisonic Technologies)
Other Datasheets by UTC

Full PDF Text Transcription

Click to expand full text
UNISONIC TECHNOLOGIES CO., LTD U74AHC1G74 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SOP-8 CMOS IC MSOP-8  DESCRIPTION The UTC U74AHC1G74 is a single positive-edge-triggered D-type flip-flop. A low level at the preset ( PRE ) or clear ( CLR ) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,data at the D input can be changed without affecting the levels at the outputs.
Published: |