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U74AHC1G74 Datasheet Preview

U74AHC1G74 Datasheet

SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP

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UNISONIC TECHNOLOGIES CO., LTD
U74AHC1G74
SINGLE
POSITIVE-EDGE-TRIGGERED
D-TYPE FLIP-FLOP WITH
CLEAR AND PRESET
DESCRIPTION
The UTC U74AHC1G74 is a single positive-edge-triggered
D-type flip-flop.
A low level at the preset ( PRE ) or clear ( CLR ) inputs sets
or resets the outputs, regardless of the levels of the other
inputs. When PRE and CLR are inactive (high), data at the
data (D) input meeting the setup time requirements is
transferred to the outputs on the positive-going edge of the
clock pulse. Clock triggering occurs at a voltage level and is not
directly related to the rise time of the clock pulse. Following the
hold-time interval,data at the D input can be changed without
affecting the levels at the outputs.
FEATURES
* Operation voltage range: 2 ~ 5.5V
* Max tPd of 7.3 ns at 5 V
* Low static power consumption; ICC=2μA (Max.)
* ±8mA output drive at 5 V
ORDERING INFORMATION
Ordering Number
Lead Free
Halogen Free
U74AHC1G74L-S08-R
U74AHC1G74G-S08-R
Package
SOP-8
CMOS IC
SOP-8
Packing
Tape Reel
MARKING
www.unisonic.com.tw
Copyright © 2015 Unisonic Technologies Co., Ltd
1 of 5
QW-R126-027.A




UTC

U74AHC1G74 Datasheet Preview

U74AHC1G74 Datasheet

SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP

No Preview Available !

U74AHC1G74
PIN CONFIGURATION
CLK 1
D2
Q3
GND 4
8 VCC
7 PRE
6 CLR
5Q
CMOS IC
FUNCTION TABLE (each gate)
INPUTS
OUTPUTS
PRE
L
H
L
H
H
H
CLR
H
L
L
H
H
H
CLK
X
X
X
L
DQQ
XH
L
XL H
X
H (Note)
H (Note)
HH
L
LLH
X Q0 Q0
Note: This configuration is nonstable; that is, it does not persist when PRE or CLR returns to its inactive (high)
level.
LOGIC DIAGRAM (positive logic)
7
PRE
CLK 2
C
C
2
D
6
CLR
C
TG
C
C
TG
C
C
TG
C
C
TG
C
5
Q
3
Q
UNISONIC TECHNOLOGIES CO., LTD
www.unisonic.com.tw
2 of 5
QW-R126-027.A


Part Number U74AHC1G74
Description SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
Maker UTC
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