UC2823A Datasheet | Unitrode

FEATURES - - - - - - - - - Improved versions of the UC3823/UC3825 PWMs patible with Voltage or Current-Mode Topologies Practical Operation at Switching Frequencies to 1MHz 50ns Propagation Delay to Output High Current Dual Totem Pole Outputs (2A Peak) Trimmed Oscillator Discharge Current Low 100µA Startup Current Pulse-by-Pulse Current Limiting parator Latched Overcurrent parator With Full Cycle Restart DESCRIPTION The UC3823A & B and the UC3825A & B family of PWM control ICs are improved versions of the standard UC3823 & UC3825 family. Performance enhancements have been made to several of the circuit blocks. Error amplifier gain bandwidth product is 12MHz while input offset voltage is 2m V. Current limit threshold is guaranteed to a tolerance of 5%. Oscillator discharge current is specified at 10m A for accurate dead time control. Frequency accuracy is improved to 6%. Startup supply current, typically 100µA, is ideal for off-line applications. The output drivers are redesigned to actively sink current during UVLO at no expense to the startup current specification. In addition each output is capable of 2A peak currents during transitions. Functional improvements have also been implemented in this family. The UC3825 shutdown parator is now a high-speed overcurrent parator with a threshold of 1.2V. The overcurrent parator sets a latch that ensures full discharge of the soft start capacitor before allowing a restart. While the fault latch is set, the outputs are in the low state. In the event of continuous faults, the soft start capacitor is fully charged before discharge to insure that the fault frequency does not exceed the designed soft start period. The UC3825 Clock pin has bee CLK/LEB. This pin bines the functions of clock output and leading edge blanking adjustment and has been buffered for easier interfacing. continued BLOCK DIAGRAM - Note: 1823A,B Version Toggles Q and Q are always low UDG-95101 9/95 DESCRIPTION (cont.) The UC3825A,B has dual alternating...