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P2V28S20DTP-7 - 128Mb SDRAM

This page provides the datasheet information for the P2V28S20DTP-7, a member of the P2V 128Mb SDRAM family.

Description

P2V28S20ATP is organized as 4-bank x 8,388,608-word x 4-bit Synchronous DRAM with LVTTL interface and P2V28S30ATP is organized as 4-bank x 4,194,304-word x 8-bit and P2V28S40ATP is organized as 4-bank x 2,097, 152-word x 16-bit.

All inputs and outputs are referenced to the rising edge of CLK.

Features

  • ITEM tCLK tRAS tRCD tAC tRC Icc1 Clock Cycle Time (Min. ) CL=2 CL=3 -7 7ns 45ns CL=2 CL=3 V28S20D 20ns 5.4ns 63ns 85mA 85mA 85mA 1mA P2V28S20/30/40ATP -75 -8 10ns 7.5ns 45ns 20ns 6ns 5.4ns 67.5ns 85mA 85mA 85mA 1mA 10ns 8ns 48ns 20ns 6ns 6ns 70ns 85mA 85mA 85mA 1mA Active to Precharge Command Period (Min. ) (Min. ) Row to Column Delay Access Time from CLK Ref /Active Command Period Operation Current (Single Bank) (Max. ) (Min. ) (Max. ) V28S30D V28S40D -7,-75,-8 Icc6 Self Refresh Current (Max. ).

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Datasheet preview – P2V28S20DTP-7

Datasheet Details

Part number P2V28S20DTP-7
Manufacturer Vanguard International Semiconductor
File Size 652.38 KB
Description 128Mb SDRAM
Datasheet download datasheet P2V28S20DTP-7 Datasheet
Additional preview pages of the P2V28S20DTP-7 datasheet.

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Full PDF Text Transcription

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128Mb Synchronous DRAM P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT) P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT) P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT) 128Mb SDRAM Specification P2V28S20DTP-7,-75,-8 P2V28S30DTP-7,-75,-8 P2V28S40DTP-7,-75,-8 MIRA TECHNOLOGY INC. 8F., 68, SEC.3, NANKING E. RD. , TAIPEI, TAIWAN, R.O.C. TEL:886-2-25170055.25170066 FAX:886-2-25174575 JULY.2000 Rev.2.
Published: |