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TRU050 Datasheet Preview

TRU050 Datasheet

Complete VCXO based Phase-Locked Loop

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TRU050
Complete VCXO based Phase-Locked Loop
Features
The TRU050, VCXO based PLL
Description
Output Frequencies to 65.536 MHz
5.0 V or 3.3Vdc Operation
Tri-State Output
Holdover on Loss of Signal Alarm
VCXO with CMOS Outputs
0/70°or –40/85°C Temperature Range
Ceramic SMD Package
RoHS/Lead Free Compliant Versions
Applications
The VI TRU050 is a user-configurable crystal-based
PLL integrated circuit. It includes a digital phase
detector, op-amp, VCXO and additional integrated
functions for use in digital synchronization
applications. Loop filter software is available as well
SPICE models for circuit simulation.
Frequency Translation
Clock Smoothing
NRZ Clock Recovery
DSLAM, ADM, ATM, Aggregation, Optical
Switching/Routing, Base Station
Low Jitter PLL’s
Figure 1. TRU050 Block Diagram
Vectron International, 267 Lowell Rd, Unit 102, Hudson NH 03051-4916
Page 1 of 14
Tel: 1-88-VECTRON-1 Web: www.vectron.com
Rev: 4/12/2016




Vectron

TRU050 Datasheet Preview

TRU050 Datasheet

Complete VCXO based Phase-Locked Loop

No Preview Available !

TRU050, VCXO Based PLL
Performance Characteristics
Table 1. Electrical Performance
Parameter
Symbol Min
Typical Maximum
Units
Output Frequency (ordering option)
Out 1, 5V option
1.000
65.636
MHz
Out 1, 3.3V option
Supply Voltage 1
+5
1.000
51.840
VDD
4.5
5.0
5.5
MHz
V
+3.3
3.0 3.3
3.6
V
Supply Current
Output Logic Levels
Output Logic High2
Output Logic Low2
Output Transition Times
Rise Time2
Fall Time2
Input Logic Levels
Output Logic High2
Output Logic Low2
Loss of Signal Indication
Output Logic High2
Output Logic Low2
Nominal Frequency on Loss of Signal
IDD
VOH 2.5
VOL
tR
tF
VIH 2.0
VIL
VOH 2.5
VOL
65 mA
V
0.5 V
5 ns
5 ns
V
0.5 V
V
0.5 V
Output 1
Output 2
Symmetry or Duty Cycle3
±75 ppm
±75 ppm
Out 1
SYM1
40/60
%
Out 2
SYM2
45/55
%
RCLK
RCLK
40/60
%
Absolute Pull Range, ordering option
over operating temp, aging, power supply
variations
APR
±50
±80
±100
ppm
Test Conditions for APR (+5V option)
Test Conditions for APR (+3.3V option)
Gain Transfer
VC 0.5
4.5
VC 0.3
3.0
Positive
V
V
Phase Detector Gain
+5V option
0.53 rad/V
+3.3V Option
0.35 rad/V
Operating temperature, ordering option
0/70 or –40/85
°C
Control Voltage Leakage Current
IVCXO
±1 uA
1. A good quality 0.01uF in parrallel with a 0.1 uf capacitor should be located as close to pin 16 to ground as possible.
2. Figure 1 defines these parameters. Figure 2 illustrates the equivalent five-gate TTL load and operating conditions under which these parameters are
tested and specified. Loads greater than 15 pF will adversely effect rise/fall time and duty cycle.
3. Symmetry is defined as (ON TIME/PERIOD with Vs=-1.4 V for both 5V and 3.3V operation.
80%
1.4V
20%
TR TF
On Time
Period
IDD
VDD + .1µF .01µF
-
16
1
IC
VC
+
-
650
3
15pF
1.8k
Figure 2. Output Waveform
Figure 3. OUT1, OUT2, RDATA and RCLK
Test Conditions (25±5°C)
Vectron International, 267 Lowell Rd, Unit 102, Hudson NH 03051-4916
Page 2 of 14
Tel: 1-88-VECTRON-1 Web: www.vectron.com
Rev: 4/12/2016


Part Number TRU050
Description Complete VCXO based Phase-Locked Loop
Maker Vectron
Total Page 14 Pages
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