DG408MIL, DG409MIL
Vishay Siliconix
8-Ch/Dual 4-Ch High-Performance CMOS Analog Multiplexers
DESCRIPTION
The DG408 is an 8 channel single-ended analog multiplexer
designed to connect one of eight inputs to a common output
as determined by a 3-bit binary address (A0, A1, A2). The
DG409 is a dual 4 channel differential analog multiplexer
designed to connect one of four differential inputs to a
common dual output as determined by its 2-bit binary
address (A0, A1). Break-before-make switching action
protects against momentary crosstalk between adjacent
channels.
An on channel conducts current equally well in both
directions. In the off state each channel blocks voltages up
to the power supply rails. An enable (EN) function allows the
user to reset the multiplexer/demultiplexer to all switches off
for stacking several devices. All control inputs, address (Ax)
and enable (EN) are TTL compatible over the full specified
operating temperature range.
Applications for the DG408, DG409 include high speed data
acquisition, audio signal switching and routing, ATE
systems, and avionics. High performance and low power
dissipation make them ideal for battery operated and
remote instrumentation applications.
Designed in the 44 V silicon-gate CMOS process, the
absolute maximum voltage rating is extended to 44 V.
Additionally, single supply operation is also allowed. An
epitaxial layer prevents latchup.
For additional information please see Technical Article
TA201.
FEATURES
• Low on-resistance - RDS(on): 100
• Low charge injection - Q: 20 pC
• Fast transition time - tTRANS: 160 ns
• Low power - ISUPPLY: 10 μA
• Single supply capability
• 44 V supply max. rating
• TTL compatible logic
BENEFITS
• Reduced switching errors
• Reduced glitching
• Improved data throughput
• Reduced power consumption
• Increased ruggedness
• Wide supply ranges (± 5 V to ± 20 V)
APPLICATIONS
• Data acquisition systems
• Audio signal routing
• ATE systems
• Battery powered systems
• High rel systems
• Single supply systems
• Medical instrumentation
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
DG408
CerDIP
Top View
A0 1
16 A1
EN 2 Decoders/Drivers 15 A2
V-
3
GND
14
S1 4
S2 5
V+
13
12 S5
S3 6
11 S6
S4 7
10 S7
D8
9 S8
DG409
CerDIP
Top View
A0 1
16 A1
EN 2 Decoders/Drivers 15 GND
V-
3
V+
14
S1a 4
S2a 5
13 S1b
12 S2b
S3a 6
11 S3b
S4a 7
10 S4b
Da 8
9 Db
Document Number: 67952
S11-1003-Rev. A, 23-May-11
www.vishay.com
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This document is subject to change without notice.
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