SI1317DL Datasheet Text
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SPICE Device Model Si1317DL
Vishay Siliconix
P-Channel 20 V (D-S) MOSFET
DESCRIPTION
The attached SPICE model describes the typical electrical characteristics of the p-channel vertical DMOS. The subcircuit model is extracted and optimized over the
- 55 °C to + 125 °C temperature ranges under the pulsed 0 V to 5 V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device.
CHARACTERISTICS
- P-Channel Vertical DMOS
- Macro Model (Subcircuit Model)
- Level 3 MOS
- Apply for both Linear and Switching Application
- Accurate over the
- 55 °C to + 125 °C Temperature Range
- Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics
SUBCIRCUIT MODEL SCHEMATIC
D
CGD
M2 G RG Gy +
- ETCV Gx CGS M1
R1 3
DBD
S
Note This document is intended as a SPICE modeling guideline and does not constitute a mercial product datasheet. Designers should refer to the appropriate datasheet of the same number for guaranteed specification limits.
Document Number: 67525 S11-0395-Rev. A, 14-Mar-11
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Datasheet pdf
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This datasheet is subject to change without notice. THE PRODUCT DESCRIBED HEREIN AND THIS DATASHEET ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT .vishay./doc?91000
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