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SI2324DS Datasheet

N-Channel MOSFET

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SPICE Device Model Si2324DS
Vishay Siliconix
N-Channel 100 V (D-S) MOSFET
DESCRIPTION
The attached SPICE model describes the typical electrical
characteristics of the n-channel vertical DMOS. The
subcircuit model is extracted and optimized over the - 55 °C
to + 125 °C temperature ranges under the pulsed 0 V to
10 V gate drive. The saturated output impedance is best fit
at the gate bias near the threshold voltage. A novel
gate-to-drain feedback capacitance network is used to
model the gate charge characteristics while avoiding
convergence difficulties of the switched Cgd model. All
model parameter values are optimized to provide a best fit
to the measured electrical data and are not intended as an
exact physical interpretation of the device.
CHARACTERISTICS
• N-Channel Vertical DMOS
• Macro Model (Subcircuit Model)
• Level 3 MOS
• Apply for both Linear and Switching Application
• Accurate over the - 55 °C to + 125 °C Temperature Range
• Model the Gate Charge, Transient, and Diode Reverse
Recovery Characteristics
SUBCIRCUIT MODEL SCHEMATIC
D
CGD
M2 R1
Gy Gx 3 DBD
G –+
RG
ETCV
CGS
M1
S
Note
• This document is intended as a SPICE modeling guideline and does not constitute a commercial product datasheet. Designers should refer
to the appropriate datasheet of the same number for guaranteed specification limits.
Document Number: 63245
S11-1189-Rev. A, 27-Jun-11
www.vishay.com
1
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Datasheet pdf - http://www.DataSheet4U.net/


Vishay Intertechnology Electronic Components Datasheet

SI2324DS Datasheet

N-Channel MOSFET

No Preview Available !

www.DataSheet.co.kr
SPICE Device Model Si2324DS
Vishay Siliconix
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
Static
Gate-Source Threshold Voltage
Drain-Source On-State Resistancea
Forward Transconductancea
Body Diode Voltage
Dynamicb
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Total Gate Charge
SYMBOL
TEST CONDITIONS
VGS(th)
RDS(on)
gfs
VSD
VDS = VGS, ID = 250 μA
VGS = 10 V, ID = 1.5 A
VGS = 6 V, ID = 1 A
VDS = 20 V, ID = 4.6 A
IS = 1.3 A
Ciss
Coss
Crss
Qg
VDS = 20 V, VGS = 0 V, f = 1 MHz
VDS = 50 V, VGS = 10 V, ID = 1.6 A
Gate-Source Charge
Qgs VDS = 50 V, VGS = 4.5 V, ID = 1.6 A
Gate-Drain Charge
Qgd
Notes
a. Pulse test; pulse width 300 μs, duty cycle 2 %.
b. Guaranteed by design, not subject to production testing.
SIMULATED MEASURED
DATA
DATA
1.8
0.199
0.222
3
0.79
-
0.195
0.222
2
0.80
190 190
22 22
15 13
4.1 5.2
2.5 2.9
0.75 0.75
1.4 1.4
UNIT
V
S
V
pF
nC
www.vishay.com
2
Document Number: 63245
S11-1189-Rev. A, 27-Jun-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Datasheet pdf - http://www.DataSheet4U.net/


Part Number SI2324DS
Description N-Channel MOSFET
Maker Vishay Siliconix
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SI2324DS Datasheet PDF






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