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SI2399DS Datasheet

P-Channel MOSFET

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SPICE Device Model Si2399DS
Vishay Siliconix
P-Channel 20 V (D-S) MOSFET
DESCRIPTION
The attached SPICE model describes the typical electrical
characteristics of the p-channel vertical DMOS. The
subcircuit model is extracted and optimized over the - 55 °C
to + 125 °C temperature ranges under the pulsed 0 V to 5 V
gate drive. The saturated output impedance is best fit at the
gate bias near the threshold voltage. A novel gate-to-drain
feedback capacitance network is used to model the gate
charge characteristics while avoiding convergence
difficulties of the switched Cgd model. All model parameter
values are optimized to provide a best fit to the measured
electrical data and are not intended as an exact physical
interpretation of the device.
CHARACTERISTICS
• P-Channel Vertical DMOS
• Macro Model (Subcircuit Model)
• Level 3 MOS
• Apply for both Linear and Switching Application
• Accurate over the - 55 °C to + 125 °C Temperature Range
• Model the Gate Charge, Transient, and Diode Reverse
Recovery Characteristics
SUBCIRCUIT MODEL SCHEMATIC
D
CGD
M2 R1
Gy Gx 3 DBD
G +–
RG
ETCV
CGS
M1
S
Note
This document is intended as a SPICE modeling guideline and does not constitute a commercial product datasheet. Designers should refer to
the appropriate datasheet of the same number for guaranteed specification limits.
Document Number: 67605
S11-0398-Rev. A, 14-Mar-11
www.vishay.com
1
This datasheet is subject to change without notice.
THE PRODUCT DESCRIBED HEREIN AND THIS DATASHEET ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Datasheet pdf - http://www.DataSheet4U.net/


Vishay Intertechnology Electronic Components Datasheet

SI2399DS Datasheet

P-Channel MOSFET

No Preview Available !

www.DataSheet.co.kr
SPICE Device Model Si2399DS
Vishay Siliconix
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
SIMULATED MEASURED
DATA
DATA
Static
Gate-Source Threshold Voltage
Drain-Source On-State Resistancea
Forward Transconductancea
Diode Forward Voltage
Dynamicb
VGS(th)
RDS(on)
gfs
VSD
VDS = VGS, ID = - 250 μA
VGS = - 10 V, ID = - 5.1 A
VGS = - 4.5 V, ID = - 4.5 A
VDS = - 5 V, ID = - 4.6 A
IS = - 4.1 A
0.83
0.029
0.035
13
- 0.81
-
0.028
0.037
15
- 0.80
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Total Gate Charge
Ciss
Coss
Crss
Qg
VDS = - 10 V, VGS = 0 V, f = 1 MHz
VDS = - 10 V, VGS = - 4.5 V, ID = - 5.1 A
834
181
154
9
6
835
180
155
10
6.4
Gate-Source Charge
Gate-Drain Charge
Qgs VDS = - 10 V, VGS = - 2.5 V, ID = - 5.1 A
Qgd
1.7
3.4
1.7
3.4
Notes
a. Pulse test; pulse width 300 μs, duty cycle 2 %.
b. Guaranteed by design, not subject to production testing.
UNIT
V
S
V
pF
nC
www.vishay.com
2
Document Number: 67605
S11-0398-Rev. A, 14-Mar-11
This datasheet is subject to change without notice.
THE PRODUCT DESCRIBED HEREIN AND THIS DATASHEET ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Datasheet pdf - http://www.DataSheet4U.net/


Part Number SI2399DS
Description P-Channel MOSFET
Maker Vishay Siliconix
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SI2399DS Datasheet PDF






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