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SI5945DU Datasheet

Dual P-Channel 20-V (D-S) MOSFET

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SPICE Device Model Si5945DU
Vishay Siliconix
Dual P-Channel 20-V (D-S) MOSFET
CHARACTERISTICS
P-Channel Vertical DMOS
Macro Model (Subcircuit Model)
Level 3 MOS
Apply for both Linear and Switching Application
Accurate over the 55 to 125°C Temperature Range
Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the p-channel vertical DMOS. The subcircuit
model is extracted and optimized over the 55 to 125°C
temperature ranges under the pulsed 0-V to 5-V gate drive. The
saturated output impedance is best fit at the gate bias near the
threshold voltage.
A novel gate-to-drain feedback capacitance network is used to model
the gate charge characteristics while avoiding convergence difficulties
of the switched Cgd model. All model parameter values are optimized
to provide a best fit to the measured electrical data and are not
intended as an exact physical interpretation of the device.
SUBCIRCUIT MODEL SCHEMATIC
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
Document Number: 74129
S-51988Rev. A, 03-Oct-05
www.vishay.com
1


Vishay Intertechnology Electronic Components Datasheet

SI5945DU Datasheet

Dual P-Channel 20-V (D-S) MOSFET

No Preview Available !

SPICE Device Model Si5945DU
Vishay Siliconix
SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED)
Parameter
Symbol
Test Condition
Static
Gate Threshold Voltage
On-State Drain Currenta
Drain-Source On-State Resistancea
Forward Transconductancea
Diode Forward Voltagea
Dynamicb
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Total Gate Charge
VGS(th)
ID(on)
rDS(on)
gfs
VSD
Ciss
Coss
Crss
Qg
VDS = VGS, ID = 250μA
VDS ≤ −5V, VGS = 4.5V
VGS = 4.5V, ID = 3.3 A
VGS = 2.5V, ID = 2.8 Α
VGS = 1.8V, ID = 0.76 Α
VDS = 10V, ID = 3.3 A
IS = 1A, VGS = 0 V
VDS = 10 V, VGS = 0 V, f = 1 MHz
VDS = 10 V, VGS = 8 V, ID = 4.6 A
Gate-Source Charge
Gate-Drain Charge
Qgs
Qgd
Notes
a. Pulse test; pulse width 300 μs, duty cycle 2%.
b. Guaranteed by design, not subject to production testing.
VDS = 10 V, VGS = 4.5 V, ID = 4.6 A
Simulated Measured
Data
Data
0.80
60
0.063
0.082
0.107
11
0.78
0.060
0.083
0.108
9
0.80
589 455
103 105
57 65
8.4 9.1
5 5.5
0.75
0.75
1.5 1.5
Unit
V
A
Ω
S
V
pF
nC
www.vishay.com
2
Document Number: 74129
S-51988Rev. A, 03-Oct-05


Part Number SI5945DU
Description Dual P-Channel 20-V (D-S) MOSFET
Maker Vishay Siliconix
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