2.488Gb/s SONET / SDH
16:1 Mux with Clock Generator and Laser Driver
Advance Product Information
The VSC8161 takes incoming 16-bit wide data at 155 MHz, D0 through D15, and converts it into a serial
data stream, with D0 transmitted ﬁrst. CLK16 is the 155MHz low-speed clock output which is created by divid-
ing the internally generated 2.488 GHz clock by 16. The upstream device should use the CLK16 as its internal
reference and to register its low-speed data and parity output signals (See Fig 1). Care needs to be taken to meet
the data setup and hold timing on the parallel data.
Figure 1: VSC8161 Parallel Data Interface
The timing relationship between the VSC8161 and the upstream device is described by the waveforms in
Fig. 5 and the associated parameters: tD, tDSU, and tDH appearing in Table 1.
The polarity of the serialized data can be inverted by the assertion of the DINVERT input. In either case,
however, the signal is retimed prior to the Laser Driver section of the VSC8161.
The clock multiplier is fully integrated. No external components are needed. Jitter Generation of the clock
multiplier meets the requirement of Bellcore’s GR-253 (SONET) document. As in all of the frequency synthe-
sizers that employ a PLL, it is important to choose REFCK to be as jitter-free as possible.
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