2.488 Gbits/sec SONET/SDH
FEC Encoder and Decoder (CODEC) Chipset
Advance Product Information
The device utilizes two 16 bit differential PECL I/O ports to interface with a high speed Multiplexer and a
Demultiplexer. For the Encoder, the 1:16 Demultiplexer is used to convert the incoming 2.5 Gbps STS-48 infor-
mation to a 16 bit parallel data at 155 MHz to interface with the VSC9210. After the encoding process, the 16 bit
parallel output data from the VSC9210 is obtained at 165 MHz and is converted to a 2.65 Gbps data stream using
the 16:1 Multiplexer. In the case of the Decoder configuration, the Demultiplexer operates on a 2.65 Gbps data
stream while the Multiplexer provides the 2.5 Gbps STS-48 information stream. Clock dividers are incorporated
within the VSC9210 to provide control of an external PLL circuit for synthesizing the necessary reference clock
for the Multiplexer. In the case of the Bypass mode, the input and output rates are identical and both the Multi-
plexer and Demultiplexer operate at 2.5 Gbps. See Figure 1 for System Diagram detail.
The User Channel is an 8 bit TTL interface operating at 1.296 MHz resulting in an aggregate data rate of
10.368 Mbps. This data channel is encoded and decoded along with the 16-bit STS data, i.e. errors occurring in
this User Channel are also corrected.
The VSC9210 can be operated at or below unencoded and encoded data rates of 155Mbs and 165Mbs
respectively. The ratio of the two input clocks (INCLK and OUTCLK) must be 15/16 for Encoder operation, and
16/15 for Decoder operation.
VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52256-0, Rev. 2.3