W3EG264M72AFSRXXXD3 Key Features
- JEDEC design specifications Phase-lock loop (PLL) clock driver to reduce loading Bi-directional data strobes (DQS) Differ
- Part: W3EG264M72AFSRXXXD3
- Manufacturer: White Electronic
- Size: 253.21 KB
Related White Electronic Datasheets
| Part Number | Description |
|---|---|
| W3EG264M72EFSUXXXD4 | 1GB - 2x64Mx72 DDR SDRAM |
| W3EG264M64EFSU-D4 | 1GB - 2x64Mx64 DDR SDRAM |
| W3EG264M64ETSR-JD3 | 1GB - 2x64Mx64 DDR SDRAM REGISTERED |
| W3EG2128M72AFSR-AD3 | 2GB - 2x128Mx72 DDR SDRAM REGISTERED ECC |
| W3EG2128M72AFSR-D3 | 2GB - 2x128Mx72 DDR SDRAM REGISTERED ECC |