W3EG7262S-JD3 Features
* Double-data-rate architecture DDR200 and DDR266
* JEDEC design specified Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2.5 (clock) Programmable Burst Length (2,4,8) Programmable Burst type (sequential & interleave) Edge aligned data output,
W3EG7262S-D3_WhiteElectronic.pdf
Datasheet Details
W3EG7262S-JD3, W3EG7262S-D3
White Electronic
244.43 KB
512mb - 2x32mx72 ddr sdram unbuffered.
This datasheet PDF includes multiple part numbers: W3EG7262S-JD3, W3EG7262S-D3.
Please refer to the document for exact specifications by model.
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W3EG7262S-JD3 Distributor
