WED3EG7218S-JD3 Datasheet PDF - White Electronic Designs 128MB - 16Mx72 DDR SDRAM UNBUFFERED Specs

WED3EG7218S-JD3 - 128MB - 16Mx72 DDR SDRAM UNBUFFERED

Datasheet Summary

Description

The WED3EG7218S is a 16Mx72 Double Data Rate SDRAM memory module based on 128Mb DDR SDRAM component.

The module consists of nine 16Mx8 DDR SDRAMs in 66 pin TSOP packages mounted on a 184 pin FR4 substrate.

Synchronous design allows precise cycle control with the use of system clock.

Features

Double-data-rate architecture DDR200, DDR266, DDR333 and DDR400.
JEDEC design speciﬁed BI-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2.5 (clock) Programmable Burst Length (2,4,8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input. Auto and self refresh Serial presence detect Power supply:.
VCC = VCCQ = 2.5V±0.2V (100, 133 and 166MHz).
VCC = VCCQ = 2.6V±0.1V (200MHz).

Datasheet Details

Part number	WED3EG7218S-JD3
Manufacturer	White Electronic Designs
File Size	237.03 KB
Description	128MB - 16Mx72 DDR SDRAM UNBUFFERED
Datasheet	WED3EG7218S-JD3 Datasheet
Additional preview pages of the WED3EG7218S-JD3 datasheet.

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Full PDF Text Transcription

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www.datasheet4u.com White Electronic Designs WED3EG7218S-JD3 PRELIMINARY* 128MB – 16Mx72 DDR SDRAM UNBUFFERED FEATURES Double-data-rate architecture DDR200, DDR266, DDR333 and DDR400 • JEDEC design speciﬁed BI-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2.5 (clock) Programmable Burst Length (2,4,8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input. Auto and self refresh Serial presence detect Power supply: • VCC = VCCQ = 2.5V±0.2V (100, 133 and 166MHz) • VCC = VCCQ = 2.6V±0.1V (200MHz) * This product is under development, is not qualiﬁed or characterized and is subject to change without notice.

Published: Apr 7, 2009 |