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WV3HG128M72EEU-PD4 - 1GB - 128Mx72 DDR2 SDRAM UNBUFFERED

General Description

The WV3HG128M72EEU is a 128Mx72 Double Data Rate DDR2 SDRAM high density module.

This memory module consists of nine 128Mx8 bit DDR2 Synchronous DRAMs in FBGA packages, mounted on a 200-pin SO-DIMM FR4 substrate.

This product is under development, is not qualified or characterized and is subjec

Key Features

  • Unbuffered 200-pin (SO-DIMM) small-outline dual in-line memory module Support ECC detection and correction Fast data transfer rates: PC2-6400.
  • , PC2-5300.
  • , PC2-4200 and PC2-3200 VCC = VCCQ = 1.8V ±0.1V VCCSPD = 1.7V to 3.6V JEDEC standard 1.8V I/O (SSTL_18-compatible) Differential data strobe (DQS, DQS#) option Differential clock input (CK,CK#) Four-bit prefetch architecture Multiple internal device banks for concurrent operation Programmable CAS# latency (CL): 3 4, 5.
  • , and 6.
  • Adj.

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Datasheet Details

Part number WV3HG128M72EEU-PD4
Manufacturer White Electronic Designs
File Size 212.37 KB
Description 1GB - 128Mx72 DDR2 SDRAM UNBUFFERED
Datasheet download datasheet WV3HG128M72EEU-PD4 Datasheet

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The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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White Electronic Designs WV3HG128M72EEU-PD4 ADVANCED* 1GB – 128Mx72 DDR2 SDRAM UNBUFFERED, SO-DIMM w/PLL FEATURES Unbuffered 200-pin (SO-DIMM) small-outline dual in-line memory module Support ECC detection and correction Fast data transfer rates: PC2-6400*, PC2-5300*, PC2-4200 and PC2-3200 VCC = VCCQ = 1.8V ±0.1V VCCSPD = 1.7V to 3.6V JEDEC standard 1.8V I/O (SSTL_18-compatible) Differential data strobe (DQS, DQS#) option Differential clock input (CK,CK#) Four-bit prefetch architecture Multiple internal device banks for concurrent operation Programmable CAS# latency (CL): 3 4, 5*, and 6* Adjustable data-output drive strength 7.