Description
ED0-15 SD0-15 A0-16 SWE#1-2 SCS#1-2 OE# VCC GND NC EWE#1-2 ECS#1-2 EEPROM Data Inputs/Outputs SRAM Data Inputs/Outputs Address Inputs SRAM Write Enable SRAM Chip Selects Output Enable Power Supply Ground Not Connected EEPROM Write Enable EEPROM Chip Select
BLOCK DIAGRAM
SWE 1 # SCS 1 # OE# A0-16 12
Features
- Access Times of 35ns (SRAM) and 150ns (EEPROM) Access Times of 45ns (SRAM) and 120ns (EEPROM) Access Times of 70ns (SRAM) and 300ns (EEPROM) Packaging.
- 66 pin, PGA Type, 1.075" square HIP, Hermetic Ceramic HIP (H1) (Package 400).
- 68 lead, Hermetic CQFP (G2T), 22mm (0.880") square (Package 509). Designed to fit JEDEC 68 lead 0.990" CQFJ footprint (FIGURE 2) 128Kx16 SRAM 128Kx16 EEPROM Organized as 128Kx16 of SRAM and 128Kx16 of EEPROM Memory with separate Data Buses Both blocks o.
WSE128K16-xxx Datasheet
