PCM-UIO96B Key Features
- Bidirectional operation
- Input, Output or Output with Read back
- 12mA Sink Current Generates an interrupt on signal change-of-state
- Supports 48 event sense lines
- Software selectable edge polarity for each line
- Software enabled interrupt for each line
- Change-of-state latched for each line Write-protection mask register for each 8-bit port patible with industry standard
- Each WS16C48 ASIC supports event sense lines which can generate an interrupt when an event occurs. These lines are the f
- The PCM-UIO96B can generate a system interrupt request which can be routed via a jumper block to IRQ channels 2
- 12, 14, and 15. Both WS16C48s can generate an individual interrupt; however, the interrupt requests from both chips can