25N01GVZEIG
25N01GVZEIG is 3V 1G-BIT SERIAL SLC NAND FLASH MEMORY manufactured by Winbond.
- Part of the 25N01GVSFIG comparator family.
- Part of the 25N01GVSFIG comparator family.
W25N01GVxx IG/IT
3V 1G-BIT SERIAL SLC NAND FLASH MEMORY WITH DUAL/QUAD SPI BUFFER READ & CONTINUOUS READ
Publication Release Date: May 09, 2018 Revision L
W25N01GVxx IG/IT
Table of Contents
1.
GENERAL DESCRIPTIONS............................................................................................................. 6
2.
Features
....................................................................................................................................... 6
3.
PACKAGE TYPES AND PIN CONFIGURATIONS .......................................................................... 7
3.1 Pad Configuration WSON 8x6-mm ...................................................................................... 7
3.2 Pad Description WSON 8x6-mm .......................................................................................... 7
3.3 Pin Configuration SOIC 300-mil ........................................................................................... 8
3.4 Pin Description SOIC 300-mil............................................................................................... 8
3.5 Ball Configuration TFBGA 8x6-mm (5x5 or 6x4 Ball Array) ................................................. 9
3.6 Ball Description TFBGA 8x6-mm ......................................................................................... 9
4.
PIN DESCRIPTIONS ...................................................................................................................... 10
4.1 Chip Select (/CS) ................................................................................................................ 10
4.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) .................................. 10
4.3 Write Protect (/WP)............................................................................................................. 10
4.4 HOLD (/HOLD) ............................................................................................................
