2dimm ddr zero delay buffer.
1 PIN CONFIGURATION ..1 BLOCK DIAGRAM .........2 PIN DESCRIPTION........2 5.1 5.2 6. 6.1 6.2 7. 7.1 7.2 7.3 7.4 8. 8.1 8.2 8.3 9. 10. 11. 12. Clock Outputs ... 3 Power Pi.
......1 FEATURES 1 PIN CONFIGURATION ..1 BLOCK DIAGRAM .........2 PIN DESCRIPTION........2 5.1 5.2 6. 6.1 6.2 7. 7.1 7.2 7.3 7.4 8. 8.1 8.2 8.3 9. 10. 11. 12. Clock Outputs ... 3 Power Pins........ 3 Register 5: Output Control (1 = Active, 0 = Inacti.
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