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W946432AD Datasheet Preview

W946432AD Datasheet

DDR SDRAM

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W946432AD
512K × 4 BANKS × 32 BITS DDR SDRAM
GENERAL DESCRIPTION
The W946432AD is a high-speed CMOS Double Data Rate synchronous dynamic random access
memory organized as 512K words x 4 banks x 32 bits.
A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at
the receiver. DQS is a strobe transmitted by the DDR SDRAM during READs and by the memory
controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for
WRITEs.
The W946432AD operates from a differential clock (CLK and CLK the crossing of CLK going HIGH
and CLK going LOW will be referred to as the postive edge of CLK). Commands (address and control
signals) are registered at every positive edge of CLK. Input data is registered on both edges of DQS,
and output data is referenced to both edges of DQS, as well as to both edges of CLK.
Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location
and continue for a programmed number of locations in a programmed sequence. Accesses begin with
the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The
address bits registered coincident with the ACTIVE command are used to select the bank and row to
be accessed. The address bits registered coincident with the READ or WRITE command are used to
select the bank and the starting column location for the burst access.
The DDR SDRAM provides for programmable READ or WRITE burst lengths of 2, 4 or 8 locations. An
AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is initiated at
the end of the burst access.
As with standard SDRAMs, the pipelined, multibank architecture of DDR SDRAMs allows for
concurrent operation, thereby providing high effective bandwidth by hiding row precharge and
activation time.
FEATURES
Double-data-rate architecture; two data transfers
per clock cycle
Bidirectional, data strobe (DQS) is transmitted/
received with data, to be used in capturing data
at the receiver
DQS is edge-aligned with data for READs;
center-aligned with data for WRITEs
Differential clock inputs (CLK and CLK )
DLL aligns DQ and DQS transitions with CLK
transitions
Programmable DLL on or DLL off mode
Commands entered on each positive CLK edge;
data and data mask referenced to both edges of
DQS
Four internal banks for concurrent operation
Data mask (DM) for write data
Burst lengths: 2, 4, or 8
CAS Latency: 3
AUTO PRECHARGE option for each burst
access
Auto Refresh and Self Refresh Modes
15.6us Maximum Average Periodic Refresh
Interval
2.5V (SSTL_2 compatible) I/O
VDDQ = 2.5V ± 0.2V
VDD = 2.5V ± 0.2V
PRELIMINARY DATA:9/8/00
1




Winbond

W946432AD Datasheet Preview

W946432AD Datasheet

DDR SDRAM

No Preview Available !

W946432AD
512K × 4 BANKS × 32 BITS DDR SDRAM
PIN CONFIGURATION
DQ3
VDDQ
DQ4
DQ5
VSSQ
DQ6
DQ7
VDDQ
DQ16
DQ17
VSSQ
DQ18
DQ19
VDDQ
V DD
VSS
DQ20
DQ21
VSSQ
DQ22
DQ23
VDDQ
DM0
DM2
WE
CAS
RAS
CS
BA0
BA1
1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 8180
2 79
3 78
4 77
5 76
6 75
7 74
8 73
9 72
10 71
11 70
12 69
13 68
14 67
15 66
16 65
17 64
18 63
19 62
20 61
21 60
22 59
23 58
24 57
25 56
26 55
27 54
28 53
29 52
3031 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51
DQ28
V DD Q
DQ27
DQ26
VSSQ
DQ25
DQ24
VDDQ
DQ15
DQ14
VSSQ
DQ13
DQ12
V DD Q
VSS
V DD
DQ11
DQ10
VSSQ
DQ9
DQ8
V DD Q
VREF
DM3
DM1
CLK
CLK
CKE
N.C
A8/AP
PRELIMINARY DATA:9/8/00
2


Part Number W946432AD
Description DDR SDRAM
Maker Winbond
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