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Xicor

X20C04 Datasheet Preview

X20C04 Datasheet

Nonvolatile Static RAM

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4K
X20C04
512 x 8 Bit
Nonvolatile Static RAM
FEATURES
• High reliability
—Endurance: 1,000,000 nonvolatile store
operations
—Retention: 100 years minimum
• Power-on recall
—EEPROM data automatically recalled into
SRAM upon power-up
• Lock out inadvertent store operations
• Low power CMOS
—Standby: 250µA
• Infinite EEPROM array recall, and RAM read and
write cycles
• Compatible with X2004
DESCRIPTION
The Xicor X20C04 is a 512 x 8 NOVRAM featuring a
static RAM overlaid bit-for-bit with a nonvolatile electri-
cally erasable PROM (EEPROM). The X20C04 is fabri-
cated with advanced CMOS floating gate technology
to achieve low power and wide power-supply margin.
The X20C04 features the JEDEC approved pinout for
byte-wide memories, compatible with industry stan-
dard RAMs, ROMs, EPROMs, and EEPROMs.
The NOVRAM design allows data to be easily transferred
from RAM to EEPROM (store) and EEPROM to RAM
(recall). The store operation is completed in 5ms or less
and the recall operation is completed in 5µs or less.
Xicor NOVRAMS are designed for unlimited write
operations to RAM, either from the host or recalls from
EEPROM, and a minimum 1,000,000 store operations
to the EEPROM. Data retention is specified to be
greater than 100 years.
BLOCK DIAGRAM
A3–A6
CE
OE
WE
NE
A0–A2
A7–A8
REV 1.0 6/21/00
Control
Logic
VCC Sense
EEPROM Array
Row
Select
512 x 8
SRAM
Array
www.xicor.com
Column
Select
&
I/OS
I/O0–I/O7
Characteristics subject to change without notice. 1 of 15




Xicor

X20C04 Datasheet Preview

X20C04 Datasheet

Nonvolatile Static RAM

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X20C04
PIN CONFIGURATION
Plastic CERDIP
NE 1
28 VCC
NC 2
27 WE
A7 3
26 NC
A6 4
25 A8
A5 5
24 NC
A4 6
23 NC
A3 7 X20C04 22 OE
A2 8
21 NC
A1 9
20 CE
A0 10
I/O0 11
19 I/O7
18 I/O6
I/O1 12
17 I/O5
I/O2 13
16 I/O4
VSS 14
15 I/O3
LCC
PLCC
4 3 2 1 32 31 30
A6 5
A5 6
29 A8
28 NC
A4 7
A3 8
A2 9
A1 10
X20C04
(Top View)
27 NC
26 NC
25 OE
24 NC
A0 11
23 CE
NC 12
22 I/O7
I/O0
13 21
14 15 16 17 18 19 20
I/O6
PIN NAMES
Symbol
A0–A8
I/O0–I/O7
WE
CE
OE
NE
VCC
VSS
NC
Description
Address inputs
Data input/output
Write enable
Chip enable
Output enable
Nonvolatile enable
+5V
Ground
No connect
PIN DESCRIPTIONS
Addresses (A0–A8)
The Address inputs select an 8-bit memory location
during a read or write operation.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/
write operations. When CE is HIGH, power consump-
tion is reduced.
Output Enable (OE)
The Output Enable input controls the data output buff-
ers and is used to initiate read and recall operations.
Output Enable LOW disables a store operation regard-
less of the state of CE, WE, or NE.
Data In/Data Out (I/O0–I/O7)
Data is written to or read from the X20C04 through the
I/O pins. The I/O pins are placed in the high impedance
state when either CE or OE is HIGH or when NE is LOW.
Write Enable (WE)
The Write Enable input controls the writing of data to
both the static RAM and stores to the EEPROM.
Nonvolatile Enable (NE)
The Nonvolatile Enable input controls all accesses to
the EEPROM array (store and recall functions).
DEVICE OPERATION
The CE, OE, WE and NE inputs control the X20C04
operation. The X20C04 byte-wide NOVRAM uses a 2-
line control architecture to eliminate bus contention in a
system environment. The I/O bus will be in a high
impedance state when either OE or CE is HIGH, or
when NE is LOW.
REV 1.0 6/21/00
www.xicor.com
Characteristics subject to change without notice. 2 of 15


Part Number X20C04
Description Nonvolatile Static RAM
Maker Xicor
Total Page 15 Pages
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