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Xicor

X25043 Datasheet Preview

X25043 Datasheet

Programmable Watchdog Supervisory E2PROM

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APPLICATION NOTES
AVA I L A B L E
X25043/45AN11 • AN21
4K
X25043/45
512 x 8 Bit
Programmable Watchdog Supervisory E2PROM
FEATURES
Programmable Watchdog Timer
Low VCC Detection
Reset Signal Valid to VCC = 1V
1MHz Clock Rate
512 X 8 Bits Serial E2PROM
—4 Byte Page Mode
Low Power CMOS
—50µA Standby Current
—3mA Active Current
2.7V To 5.5V Power Supply
Block LockTM
—Protect 1/4, 1/2 or all of E2PROM Array
Built-in Inadvertent Write Protection
—Power-Up/Power-Down protection circuitry
—Write Latch
—Write Protect Pin
High Reliability
—Endurance: 100,000 cycles per byte
—Data Retention: 100 Years
—ESD protection: 2000V on all pins
Available Packages
—8-Lead PDlP
—8-Lead SOIC
—14-Lead TSSOP
X25043 = Active LOW RESET
X25045 = Active HIGH RESET
DESCRIPTION
The X25043/45 combines three popular functions,
Watchdog Timer, Voltage Supervision, and E2PROM in
a single package. This combination lowers the system
cost and reduces the board space requirements.
The Watchdog Timer provides an independent protec-
tion system for microcontrollers. During a system failure,
the X25043/45 watchdog will respond with a RESET/
RESET signal after a selectable time-out interval. The
user selects the interval from three preset values. Once
selected, the interval does not change, even after cy-
cling the power.
The system is protected from low voltage conditions by
the X25043/45 low VCC detection circuits. When VCC
drops below the minimum VCC trip point, the system is
reset. Reset is asserted until VCC returns and stabilizes.
The memory portion of the X25043/45 is a CMOS 4096-
bit serial E2PROM, internally organized as 512 X 8. The
X25043/45 features a Serial Peripheral Interface (SPI)
and software protocol allowing operation on a simple
three-wire bus.
The X25043/45 utilizes Xicor’s proprietary Direct Write™
cell, providing a minimum endurance of 100,000 cycles
per byte and a minimum data retention of 100 years.
DIE PHOTOGRAPH
RESET
CONTROL
LOGIC
PROGRAMMABLE
VOLTAGE
SENSOR
SERIAL
INTERFACE
LOGIC
Direct Write™ is a trademark of Xicor, Inc.
©Xicor, Inc. 1994, 1995, 1996 Patents Pending
3844-6.5 5/9/96 T4/C2/D2 NS
4K BITS E22PROM
HHIIGGHH VVOOLLTTAAGGEE GGEENNEERRAATTOORR
AANNDD
CCOONNTTRROOLL
1
W
A
T
C
H
D
O
T
I
M
E
R
G
3844 ILL F01
Characteristics subject to change without notice




Xicor

X25043 Datasheet Preview

X25043 Datasheet

Programmable Watchdog Supervisory E2PROM

No Preview Available !

X25043/45
PIN DESCRIPTIONS
Serial Output (SO)
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked out
by the falling edge of the serial clock.
Serial Input (SI)
SI is the serial data input pin. All opcodes, byte ad-
dresses, and data to be written to the memory are input
on this pin. Data is latched by the rising edge of the serial
clock.
Serial Clock (SCK)
The Serial Clock controls the serial bus timing for data
input and output. Opcodes, addresses, or data present
on the SI pin is latched on the rising edge of the clock
input, while data on the SO pin changes after the falling
edge of the clock input.
Chip Select (CS)
When CS is HIGH, the X25043/45 is deselected and the
SO output pin is at high impedance and, unless an
internal write operation is underway, the X25043/45 will
be in the standby power mode. CS LOW enables the
X25043/45, placing it in the active power mode. It should
be noted that after power-up, a HIGH to LOW transition
on CS is required prior to the start of any operation.
Write Protect (WP)
When WP is LOW, nonvolatile writes to the X25043/45
are disabled, but the part otherwise functions normally.
When WP is held HIGH, all functions, including nonvola-
tile writes operate normally. WP going LOW while CS is
still LOW will interrupt a write to the X25043/45. If the
internal write cycle has already been initiated, WP going
LOW will have no affect on a write.
Reset (RESET, RESET)
X25043/45, RESET/RESET is an active LOW/HIGH,
open drain output which goes active whenever VCC
falls below the mimimum VCC sense level. It will remain
active until VCC rises above the minimum VCC sense
level for 200ms. RESET/RESET also goes active if
the Watchdog timer is enabled and CS remains either
HIGH or LOW longer than the Watchdog time-out
period. A falling edge of CS will reset the watchdog timer.
PIN CONFIGURATION
CS
SO
WP
VSS
X25043/45
8-LEAD DIP/SOIC
18
27
36
45
VCC
RESET/RESET
SCK
SI
CS
SO
NC
NC
NC
WP
VSS
X25043/45
14-LEAD TSSOP
1 14
2 13
3 12
4 11
5 10
69
78
VCC
RESET/RESET
NC
NC
NC
SCK
SI
3844 ILL F02.3
PIN NAMES
Symbol
CS
SO
SI
SCK
WP
VSS
VCC
RESET/RESET
Description
Chip Select Input
Serial Output
Serial Input
Serial Clock Input
Write Protect Input
Ground
Supply Voltage
Reset Output
3844 PGM T01.1
2


Part Number X25043
Description Programmable Watchdog Supervisory E2PROM
Maker Xicor
Total Page 15 Pages
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