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X25097 Datasheet Preview

X25097 Datasheet

5MHz Low Power SPI Serial E 2 PROM with IDLock TM Memory

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8K
X25097
1024 x 8 Bit
5MHz Low Power SPI Serial E2PROM with IDLockTM Memory
FEATURES
• 5MHz Clock Rate
• IDLock™ Memory
—IDLock First or Last Page, any 1/4 or Lower 1/2
of E2PROM Array
• Low Power CMOS
—<1µA Standby Current
—<3mA Active Current during Write
—<400µA Active Current during Read
• 1.8V to 3.6V, 2.7V-5.5V or 4.5V to 5.5V Operation
• Built-in Inadvertent Write Protection
—Power-Up/Power-Down Protection Circuitry
—Write Enable Latch
—Write Protect Pin
• SPI Modes (0,0 & 1,1)
• 1024 x 8 Bits
—16 Byte Page Mode
• Self-Timed Write Cycle
—5ms Write Cycle Time (Typical)
• High Reliability
—Endurance: 100,000 Cycles/Byte
—Data Retention: 100 Years
—ESD: 2000V on all pins
• 8-Lead TSSOP Package
• 8-Lead SOIC Package
• 8-Lead PDIP Package
DESCRIPTION
The X25097 is a CMOS 8K-bit serial E2PROM, internally
organized as 1024 x 8. The X25097 features a Serial
Peripheral Interface (SPI) and software protocol
allowing operation on a simple four-wire bus. The bus
signals are a clock input (SCK) plus separate data in (SI)
and data out (SO) lines. Access to the device is
controlled through a chip select (CS) input, allowing any
number of devices to share the same bus.
IDLock is a programmble locking mechanism which
allows the user to lock system ID and parametric data in
different portions of the E2PROM memory space,
ranging from as little as one page to as much as 1/2 of
the total array. The X25097 also features a WP pin that
can be used for hardwire protection of the part, disabling
all write attempts, as well as a Write Enable Latch that
must be set before a write operation can be initiated.
The X25097 utilizes Xicor’s proprietary Direct WriteTM
cell, providing a minimum endurance of 100,000 cycles
per byte and a minimum data retention of 100 years.
FUNCTIONAL DIAGRAM
SI
SO
SCK
COMMAND
DECODE
AND
CONTROL
LOGIC
CS
X
DECODE
LOGIC
DATA REGISTER
Y DECODE LOGIC
16 8
64
8K E2PROM
ARRAY
(1024 x 8)
WP WRITE CONTROL LOGIC
©Xicor, Inc. 1994, 1995, 1996 Patents Pending
7034-1.1 5/8/97 T1/C0/D0 SH
1
HIGH VOLTAGE
CONTROL
7038 FRM F01
Characteristics subject to change without notice




Xicor

X25097 Datasheet Preview

X25097 Datasheet

5MHz Low Power SPI Serial E 2 PROM with IDLock TM Memory

No Preview Available !

X25097
PIN DESCRIPTIONS
Serial Output (SO)
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked out
by the falling edge of the serial clock.
Serial Input (SI)
SI is a serial data input pin. All opcodes, byte addresses,
and data to be written to the memory are input on this
pin. Data is latched by the rising edge of the serial clock.
Serial Clock (SCK)
The Serial Clock controls the serial bus timing for data
input and output. Opcodes, addresses, or data present
on the SI pin are latched on the rising edge of the clock
input, while data on the SO pin change after the falling
edge of the clock input.
Chip Select (CS)
When CS is HIGH, the X25097 is deselected and the SO
output pin is at high impedance and unless an internal
write operation is underway, the X25097 will be in the
standby power mode. CS LOW enables the X25097,
placing it in the active power mode. It should be noted
that after power-up, a HIGH to LOW transition on CS is
required prior to the start of any operation.
Write Protect (WP)
When WP is LOW, nonvolatile writes to the X25097 are
disabled, but the part otherwise functions normally. When
WP is held HIGH, all functions, including nonvolatile
writes operate normally. WP going LOW while CS is still
LOW will interrupt a write to the X25097. If the internal
write cycle has already been initiated, WP going low will
have no affect on this write.
PIN NAMES
Symbol
CS
SO
SI
SCK
WP
VSS
VCC
NC
Description
Chip Select Input
Serial Output
Serial Input
Serial Clock Input
Write Protect Input
Ground
Supply Voltage
No Connect
7038 FRM T01
PIN CONFIGURATION
Not to scale
8 Lead SOIC/PDIP
*0.197"
CS
SO
WP
V SS
18
27
X25097
36
45
*0.244"
V CC
NC
SCK
SI
7038 FRM F02
0.122"
NC
VCC
CS
SO
8 Lead TSSOP
18
27
X25097
36
45
*SOIC Mesaurement
0.252"
SCK
SI
V SS
WP
7038 FRM F02.2
PRINCIPLES OF OPERATION
The X25097 is a 1024 x 8 E2PROM designed to interface
directly with the synchronous Serial Peripheral Interface
(SPI) of many popular microcontroller families.
The X25097 contains an 8-bit instruction register. It is
accessed via the SI input, with data being clocked in on
the rising edge of SCK. CS must be LOW and the WP
input must be HIGH during the entire operation. Table 1
contains a list of the instructions and their opcodes. All
instructions, addresses and data are transferred MSB first.
Data input is sampled on the first rising edge of SCK
after CS goes LOW. SCK is static, allowing the user to
stop the clock and then start it again to resume opera-
tions where left off.
Write Enable Latch
The X25097 contains a “Write Enable” latch. This latch
must be SET before a write operation is initiated. The
WREN instruction will set the latch and the WRDI instruc-
tion will reset the latch (Figure 4). This latch is automati-
cally reset upon a power-up condition and after the
completion of a byte or page write cycle.
2


Part Number X25097
Description 5MHz Low Power SPI Serial E 2 PROM with IDLock TM Memory
Maker Xicor
Total Page 15 Pages
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