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Xicor

X25330 Datasheet Preview

X25330 Datasheet

5MHz SPI Serial E 2 PROM with Block Lock TM Protection

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32K
X25330
4K x 8 Bit
5MHz SPI Serial E2PROM with Block LockTM Protection
FEATURES
5MHz Clock Rate
Low Power CMOS
<1µA Standby Current
<5mA Active Current
2.5V To 5.5V Power Supply
SPI Modes (0,0 & 1,1)
4K X 8 Bits
32 Byte Page Mode
Block Lock™ Protection
Protect 1/4, 1/2 or all of E2PROM Array
Programmable Hardware Write Protection
In-Circuit Programmable ROM Mode
Built-in Inadvertent Write Protection
Power-Up/Down protection circuitry
Write Enable Latch
Write Protect Pin
Self-Timed Write Cycle
5ms Write Cycle Time (Typical)
High Reliability
Endurance: 100,000 cycles
Data Retention: 100 Years
ESD protection: 2000V on all pins
Packages
8-Lead SOIC
14-Lead TSSOP
FUNCTIONAL DIAGRAM
STATUS
REGISTER
WRITE
PROTECT
LOGIC
SO
SI
SCK
CS
HOLD
COMMAND
DECODE
AND
CONTROL
LOGIC
DESCRIPTION
The X25330 is a CMOS 32K-bit serial E2PROM, inter-
nally organized as 4K x 8. The X25330 features a
Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple three-wire bus. The bus
signals are a clock input (SCK) plus separate data in
(SI) and data out (SO) lines. Access to the device is
controlled through a chip select (CS) input, allowing
any number of devices to share the same bus.
The X25330 also features two additional inputs that
provide the end user with added flexibility. By
asserting the HOLD input, the X25330 will ignore tran-
sitions on its inputs, thus allowing the host to service
higher priority interrupts. The WP input can be used as
a hardwire input to the X25330 disabling all write
attempts to the status register, thus providing a mech-
anism for limiting end user capability of altering 0, 1/4,
1/2 or all of the memory.
The X25330 utilizes Xicor’s proprietary Direct WriteTM
cell, providing a minimum endurance of 100,000
cycles and a minimum data retention of 100 years.
X DECODE
LOGIC
32
32
64
4K BYTE
ARRAY
32 X 256
32 X 256
64 X 256
WRITE
CONTROL
AND
WP
TIMING
LOGIC
Direct Writeand Block LockProtection is a trademark of Xicor, Inc.
©Xicor, Inc. 1994 - 1997 Patents Pending
7048–1.0 6/18/97 T0/C0/D0 SH
1
32 8
Y DECODE
DATA REGISTER
7037 FRM F01
Characteristics subject to change without notice




Xicor

X25330 Datasheet Preview

X25330 Datasheet

5MHz SPI Serial E 2 PROM with Block Lock TM Protection

No Preview Available !

X25330
PIN DESCRIPTIONS
Serial Output (SO)
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked
out by the falling edge of the serial clock.
Serial Input (SI)
SI is the serial data input pin. All opcodes, byte
addresses, and data to be written to the memory are
input on this pin. Data is latched by the rising edge of
the serial clock.
Serial Clock (SCK)
The Serial Clock controls the serial bus timing for data
input and output. Opcodes, addresses, or data present
on the SI pin are latched on the rising edge of the
clock input, while data on the SO pin change after the
falling edge of the clock input.
Chip Select (CS)
When CS is HIGH, the X25330 is deselected and the
SO output pin is at high impedance and unless an
internal write operation is underway, the X25330 will be
in the standby power mode. CS LOW enables the
X25330, placing it in the active power mode. It should
be noted that after power-up, a HIGH to LOW transition
on CS is required prior to the start of any operation.
Write Protect (WP)
When WP is LOW and the nonvolatile bit WPEN is “1”,
nonvolatile writes to the X25330 status register are
disabled, but the part otherwise functions normally.
When WP is held HIGH, all functions, including
nonvolatile writes operate normally. WP going LOW
while CS is still LOW will interrupt a write to the
PIN NAMES
Symbol
CS
SO
SI
SCK
WP
VSS
VCC
HOLD
NC
Description
Chip Select Input
Serial Output
Serial Input
Serial Clock Input
Write Protect Input
Ground
Supply Voltage
Hold Input
No Connect
7037 FRM T01
X25330 status register. If the internal write cycle has
already been initiated, WP going LOW will have no
affect on a write.
The WP pin function is blocked when the WPEN bit in
the status register is “0”. This allows the user to install
the X25330 in a system with WP pin grounded and still
be able to write to the status register. The WP pin func-
tions will be enabled when the WPEN bit is set “1”.
Hold (HOLD)
HOLD is used in conjunction with the CS pin to pause
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause
PIN CONFIGURATION
NOT TO SCALE
0.197"
Max
CS
SO
WP
V SS
SOIC
18
27
X25330
36
45
V CC
HOLD
SCK
SI
0.244"
TSSOP
CS 1
14 VCC
SO 2
13 HOLD
SO 3
12 HOLD
0.200"
Max
NC 4 X25330 11 NC
NC 5
10 NC
WP 6
9 SCK
VSS 7
8 SI
0.252"
7037 FRM F02
* Pin 2 and Pin 3 are internally connected. Only one CS needs to
be connected externally.
2


Part Number X25330
Description 5MHz SPI Serial E 2 PROM with Block Lock TM Protection
Maker Xicor
Total Page 14 Pages
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