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Xicor

X25640 Datasheet Preview

X25640 Datasheet

Advanced SPI Serial E2PROM With Block LockTM Protection

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APPLICATION NOTES
AVA I L A B L E
X25640AN19 • AN38 • AN41 • AN61
64K
X25640
8K x 8 Bit
Advanced SPI Serial E2PROM With Block LockTM Protection
FEATURES
1MHz Clock Rate
Low Power CMOS
—200µA Standby Current
—5mA Active Current
5 Volt Power Supply
SPI Modes (0,0 & 1,1)
8K X 8 Bits
—32 Byte Page Mode
Block Lock Protection
—Protect 1/4, 1/2 or all of E2PROM Array
Built-in Inadvertent Write Protection
—Power-Up/Power-Down protection circuitry
—Write Enable Latch
—Write Protect Pin
Self-Timed Write Cycle
—5ms Write Cycle Time (Typical)
High Reliability
—Endurance: 100,000 cycles
—Data Retention: 100 Years
—ESD protection: 2000V on all pins
8-Lead PDlP Package
14-Lead SOIC Package
DESCRIPTION
The X25640 is a CMOS 65,536-bit serial E2PROM,
internally organized as 8K x 8. The X25640 features a
Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple three-wire bus. The bus
signals are a clock input (SCK) plus separate data in (SI)
and data out (SO) lines. Access to the device is con-
trolled through a chip select (CS) input, allowing any
number of devices to share the same bus.
The X25640 also features two additional inputs that
provide the end user with added flexibility. By asserting
the HOLD input, the X25640 will ignore transitions on its
inputs, thus allowing the host to service higher priority
interrupts. The WP input can be used as a hardwire input
to the X25640 disabling all write attempts to the status
register, thus providing a mechanism for limiting end
user capability of altering 0, 1/4, 1/2 or all of the memory.
The X25640 utilizes Xicor’s proprietary Direct Write™
cell, providing a minimum endurance of 100,000 cycles
and a minimum data retention of 100 years.
FUNCTIONAL DIAGRAM
SO
SI
SCK
CS
HOLD
STATUS
REGISTER
COMMAND
DECODE
AND
CONTROL
LOGIC
WRITE
PROTECT
LOGIC
X DECODE
LOGIC
64
64
128
8K BYTE
ARRAY
64 X 256
64 X 256
128 X 256
WRITE
CONTROL
AND
WP
TIMING
LOGIC
Direct Write™ and Block Lock™ Protection is a trademark of Xicor, Inc.
©Xicor, Inc. 1994, 1995, 1996 Patents Pending
3089-1.8 6/17/96 T4/C4/D1 NS
1
32 8
Y DECODE
DATA REGISTER
3089 ILL F01
Characteristics subject to change without notice




Xicor

X25640 Datasheet Preview

X25640 Datasheet

Advanced SPI Serial E2PROM With Block LockTM Protection

No Preview Available !

X25640
PIN DESCRIPTIONS
Serial Output (SO)
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked out
by the falling edge of the serial clock.
Serial Input (SI)
SI is the serial data input pin. All opcodes, byte
addresses, and data to be written to the memory are
input on this pin. Data is latched by the rising edge of the
serial clock.
Serial Clock (SCK)
The Serial Clock controls the serial bus timing for data
input and output. Opcodes, addresses, or data present
on the SI pin are latched on the rising edge of the clock
input, while data on the SO pin change after the falling
edge of the clock input.
Chip Select (CS)
When CS is HIGH, the X25640 is deselected and the SO
output pin is at high impedance and unless an internal
write operation is underway, the X25640 will be in the
standby power mode. CS LOW enables the X25640,
placing it in the active power mode. It should be noted
that after power-up, a HIGH to LOW transition on CS is
required prior to the start of any operation.
Write Protect (WP)
When WP is LOW and the nonvolatile bit WPEN is high,
nonvolatile writes to the X25640 status register are
disabled, but the part otherwise functions normally.
When WP is held HIGH, all functions, including nonvola-
tile writes operate normally. WP going LOW while CS is
still LOW will interrupt a write to the X25640 status
register. If the internal write cycle has already been
initiated, WP going LOW will have no affect on a write.
The WP pin function is blocked when the WPEN bit in
the status register is LOW. This allows the user to install
the X25640 in a system with WP pin grounded and still
be able to write to the status register. The WP pin
functions will be enabled when the WPEN bit is set “1”.
Hold (HOLD)
HOLD is used in conjunction with the CS pin to select the
device. Once the part is selected and a serial sequence is
underway, HOLD may be used to pause the serial com-
munication with the controller without resetting the serial
sequence. To pause, HOLD must be brought LOW while
SCK is LOW. To resume communication, HOLDis brought
HIGH, again while SCK is LOW. If the pause feature is not
used, HOLD should be held HIGH at all times.
PIN CONFIGURATION
CS
SO
WP
VSS
NC
NC
CS
SO
WP
VSS
NC
8-LEAD DIP
18
27
X25640
36
45
VCC
HOLD
SCK
SI
14-LEAD SOIC
1 14
2 13
3 12
4 X25640 11
5 10
69
78
NC
NC
VCC
HOLD
SCK
SI
NC
3089 ILL F02.3
PIN NAMES
Symbol
CS
SO
SI
SCK
WP
VSS
VCC
HOLD
NC
Description
Chip Select Input
Serial Output
Serial Input
Serial Clock Input
Write Protect Input
Ground
Supply Voltage
Hold Input
No Connect
3089 PGM T01
2



Part Number X25640
Description Advanced SPI Serial E2PROM With Block LockTM Protection
Maker Xicor
Total Page 14 Pages
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X25640 Datasheet PDF





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