Serial Clock (SCL)
The SCL input is used to clock all data into and out of the
Serial Data (SDA)
SDA is a true three state serial data input/output pin. Dur-
ing a read cycle, data is shifted out on this pin. During a
write cycle, data is shifted in on this pin. In all other
cases, this pin is in a high impedance state.
Chip Enable (CS)
When CS is high, the X76F128 is deselected and the
SDA pin is at high impedance and unless an internal
write operation is underway, the X76F128 will be in
standby mode. CS low enables the X76F128, placing it in
the active mode.
RST is a device reset pin. When RST is pulsed high
while CS is low the X76F128 will output 32 bits of ﬁxed
data which conforms to the standard for “synchronous
response to reset”. CS must remain LOW and the part
must not be in a write cycle for the response to reset to
occur. See Figure 11. If at any time during the response
to reset CS goes HIGH, the response to reset will be
aborted and the part will return to the standby state. The
response to reset is "mask programmable" only!
There are two primary modes of operation for the
X76F128; Protected READ and protected WRITE.
Protected operations must be performed with one of four
The basic method of communication for the device is
established by ﬁrst enabling the device (CS LOW), gen-
erating a start condition, then transmitting a command,
followed by the correct password. All parts will be
shipped from the factory with all passwords equal to ‘0’.
The user must perform ACK Polling to determine the
validity of the password, before starting a data transfer
(see Acknowledge Polling.) Only after the correct pass-
word is accepted and a ACK polling has been performed,
can the data transfer occur.
To ensure the correct communication, RST must remain
LOW under all conditions except when running a
“Response to Reset sequence”.
Data is transferred in 8-bit segments, with each transfer
being followed by an ACK, generated by the receiving
If the X76F128 is in a nonvolatile write cycle a “no ACK”
(SDA=High) response will be issued in response to load-
ing of the command byte. If a stop is issued prior to the
nonvolatile write cycle the write operation will be termi-
nated and the part will reset and enter into a standby
The basic sequence is illustrated in Figure 1.
CS Chip Select Input
Serial Data Input/Output
SCL Serial Clock Input
Vcc Supply Voltage
NC No Connect
7052 FM T01
7052 FM 02
After each transaction is completed, the X76F128 will
reset and enter into a standby mode. This will also be the
response if an unsuccessful attempt is made to access a