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X86C64 Datasheet Preview

X86C64 Datasheet

E2 Micro-Peripheral

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Preliminary Information
XZ8®6CM6ic4rocontroller Family Compatible
64K X86C64
E2 Micro-Peripheral
8192 x 8 Bit
FEATURES
CONCURRENT READ WRITE
—Dual Plane Architecture
Isolates Read/Write Functions
Between Planes
Allows Continuous Execution of Code
From One Plane While Writing in the Other
Plane
Multiplexed Address/Data Bus
—Direct Interface to Popular 8-bit
Microcontrollers, e.g. Zilog Z8 Family
High Performance CMOS
—Fast Access Time, 120 ns
—Low Power
60 mA Maximum Active
200 µA Maximum Standby
Software Data Protection
Block Protect Register
—Individually Set Write Lock Out in 1K Blocks
Toggle Bit
—Early End of Write Detection
Page Mode Write
—Allows up to 32 Bytes to be Written in
One Write Cycle
High Reliability
—Endurance: 10,000 Write Cycle
—Data Retention: 100 Years
DESCRIPTION
The X86C64 is an 8K x 8 E2PROM fabricated with
advanced CMOS Textured Poly Floating Gate Technol-
ogy. The X86C64 features a Multiplexed Address and
Data bus allowing direct interface to a variety of popular
single-chip microcontrollers operating in expanded mul-
tiplexed mode without the need for additional interface
circuitry.
The X86C64 is internally configured as two indepen-
dent 4K x 8 memory arrays. This feature provides the
ability to perform nonvolatile memory updates in one
array and continue operation out of code stored in the
other array; effectively eliminating the need for an aux-
iliary memory device for code storage.
To write to the X86C64, a three byte command
sequence must precede the byte(s) being written. The
X86C64 also provides a second generation software
data protection scheme called Block Protect. Block
Protect can provide write lockout of the entire device or
selected 1K blocks. There are eight, 1K x 8 blocks that
can be write protected individually in any combination
required by the user. Block Protect, in addition to Write
Control input, allows the different segments of the
memory to have varying degrees of alterability in nor-
mal system operation.
FUNCTIONAL DIAGRAM
CE
R/W
DS
SEL
A8–A11
AS
CONTROL
LOGIC
LX
AD
TE
CC
HO
ED
SE
WC
A12
SOFTWARE
DATA
PROTECT
A12
1K BYTES A12 1K BYTES
M
1K BYTES
1K BYTES
U
1K BYTES X 1K BYTES
1K BYTES
1K BYTES
Y DECODE
Z8® is a registered trademark of Zilog Corporation
CONCURRENT READ WRITEis a trademark of Xicor, Inc.
© Xicor, 1991 Patents Pending
3819-2.1 7/29/96 T0/C1/D1 SH
I/O & ADDRESS LATCHES AND BUFFERS
A/D0–A/D7
3819 FHD F02
1 Characteristics subject to change without notice




Xicor

X86C64 Datasheet Preview

X86C64 Datasheet

E2 Micro-Peripheral

No Preview Available !

X86C64
PIN DESCRIPTIONS
Address/Data (A/D0–A/D7)
Multiplexed low-order addresses and data. The ad-
dresses flow into the device while AS is LOW. After AS
transitions from a LOW to HIGH the addresses are
latched. Once the addresses are latched these pins input
data or output data depending on DS, R/W, and CE.
Addresses (A8–A12)
High order addresses flow into the device when AS = VIL
and are latched when AS goes HIGH.
Chip Enable (CE)
The Chip Enable input must be HIGH to enable all read/
write operations. When CE is LOW and AS is HIGH, the
X86C64 is placed in the low power standby mode.
Data Strobe (DS)
When used with a Z8 the DS input is tied directly to the
DS output of the microcontroller.
Read/Write (R/W)
When used with a Z8 the R/W input is tied directly to the
R/W output of the microcontroller.
Address Strobe (AS)
Addresses flow through the latches to address decoders
when AS is LOW and are latched when AS transitions
from a LOW to HIGH.
Device Select (SEL)
Must be connected to VSS.
Write Control (WC)
The Write Control allows external circuitry to abort a
page load cycle once it has been initiated. This input is
useful in applications in which a power failure or proces-
sor RESET could interrupt a page load cycle. In this
case, the microcontroller might drive all signals HIGH,
causing bad data to be latched into the E2PROM. If the
Write Control input is driven HIGH (before tTBLC Max)
after Read/Write (R/W) goes HIGH, the write cycle will
be aborted.
When WC is LOW (tied to VSS) the X86C64 will be
enabled to perform write operations. When WC is HIGH
normal read operations may be performed, but all at-
tempts to write to the device will be disabled.
PIN CONFIGURATION
NC
A12
NC
NC
WC
SEL
A/D0
A/D1
A/D2
A/D3
A/D4
VSS
DIP/SOIC
1 24
2 23
3 22
4 21
5 20
6 19
X86C64
7 18
8 17
9 16
10 15
11 14
12 13
VCC
R/W
AS
A8
A9
A11
DS
A10
CE
A/D7
A/D6
A/D5
3819 FHD F01
PIN NAMES
Symbol
AS
A/D0–A/D7
A8–A12
DS
R/W
CE
WC
SEL
VSS
VCC
Description
Address Strobe
Address Inputs/Data I/O
Address Inputs
Data Strobe Input
Read/Write Input
Chip Enable
Write Control
Device Select—Connect to VSS
Ground
Supply Voltage
3819 PGM T01
2


Part Number X86C64
Description E2 Micro-Peripheral
Maker Xicor
Total Page 12 Pages
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