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XC1701L Datasheet Preview

XC1701L Datasheet

Configuration PROMs

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Product Obsolete or Under Obsolescence
<
R B XC1700E, XC1700EL, and XC1700L
L Series Configuration PROMs
DS027 (v3.5) June 25, 2008
8
Product Specification
Features
One-time programmable (OTP) read-only memory
designed to store configuration bitstreams of Xilinx®
FPGAs
Simple interface to the FPGA; requires only one user
I/O pin
Cascadable for storing longer or multiple bitstreams
Programmable reset polarity (active High or active
Low) for compatibility with different FPGA solutions
XC17128E/EL, XC17256E/EL, XC1701, and XC1700L
series support fast configuration
Low-power CMOS floating-gate process
XC1700E series are available in 5V and 3.3V versions
XC1700L series are available in 3.3V only
Available in compact plastic packages: 8-pin SOIC, 8-
pin VOIC, 8-pin PDIP, 20-pin SOIC, 20-pin PLCC, 44-
pin PLCC or 44-pin VQFP
Programming support by leading programmer
manufacturers
Design support using the Xilinx Alliance and
Foundation™ software packages
Guaranteed 20 year life data retention
Lead-free (Pb-free) packaging available
Description
The XC1700 family of configuration PROMs provides an
easy-to-use, cost-effective method for storing large Xilinx
FPGA configuration bitstreams. See Figure 1 for a
simplified block diagram.
When the FPGA is in Master Serial mode, it generates a
configuration clock that drives the PROM. A short access
time after the rising clock edge, data appears on the PROM
DATA output pin that is connected to the FPGA DIN pin. The
FPGA generates the appropriate number of clock pulses to
complete the configuration. After configured, it disables the
X-Ref Target - Figure 1
VCC VPP GND
PROM. When the FPGA is in Slave Serial mode, the PROM
and the FPGA must both be clocked by an incoming signal.
Multiple devices can be concatenated by using the CEO
output to drive the CE input of the following device. The
clock inputs and the DATA outputs of all PROMs in this
chain are interconnected. All devices are compatible and
can be cascaded with other members of the family.
For device programming, either the Xilinx Alliance or
Foundation software compiles the FPGA design file into a
standard Hex format, which is then transferred to most
commercial PROM programmers.
RESET/
OE
or
OE/
RESET
CE
CLK
Address Counter
TC
CEO
EPROM
Cell
Matrix
Output
OE
DATA
DS027_01_021500
Figure 1: Simplified Block Diagram (Does Not Show Programming Circuit)
© Copyright 1998-2008 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. All other trademarks are the property of their respective owners.
DS027 (v3.5) June 25, 2008
Product Specification
www.xilinx.com
1




Xilinx

XC1701L Datasheet Preview

XC1701L Datasheet

Configuration PROMs

No Preview Available !

R Product ObsoletXeC1o7r00UE,nXdC1e7r00OELb, asnod lXeCs17c0e0LnSceeries Configuration PROMs
Pin Description
DATA
Data output is in a high-impedance state when either CE or
OE are inactive. During programming, the DATA pin is I/O.
Note that OE can be programmed to be either active High or
active Low.
CLK
Each rising edge on the CLK input increments the internal
address counter, if both CE and OE are active.
RESET/OE
When High, this input holds the address counter reset and
puts the DATA output in a high-impedance state. The
polarity of this input pin is programmable as either
RESET/OE or OE/RESET. To avoid confusion, this
document describes the pin as RESET/OE, although the
opposite polarity is possible on all devices. When RESET is
active, the address counter is held at "0", and puts the DATA
output in a high-impedance state. The polarity of this input
is programmable. The default is active High RESET, but the
preferred option is active Low RESET, because it can be
driven by the FPGAs INIT pin.
The polarity of this pin is controlled in the programmer
interface. This input pin is easily inverted using the Xilinx
HW-130 Programmer. Third-party programmers have
different methods to invert this pin.
CE
When High, this pin disables the internal address counter,
puts the DATA output in a high-impedance state, and forces
the device into low-ICC standby mode.
CEO
Chip Enable output, to be connected to the CE input of the next
PROM in the daisy chain. This output is Low when the CE and
OE inputs are both active AND the internal address counter
has been incremented beyond its Terminal Count (TC) value.
In other words: when the PROM has been read, CEO follows
CE as long as OE is active. When OE goes inactive, CEO
stays High until the PROM is reset. Note that OE can be
programmed to be either active High or active Low.
VPP
Programming voltage. No overshoot above the specified
max voltage is permitted on this pin. For normal read
operation, this pin must be connected to VCC. Failure to do
so may lead to unpredictable, temperature-dependent
operation and severe problems in circuit debugging. Do not
leave VPP floating!
VCC and GND
Positive supply and ground pins.
PROM Pinouts
Pins not listed are "no connects."
"
Pin Name
DATA
CLK
RESET/OE
(OE/RESET)
CE
GND
CEO
VPP
VCC
8-pin
PDIP
(PD8/
PDG8)
SOIC
(SO8/
SOG8)
VOIC
(VO8/
VOG8)
20-pin
SOIC
(SO20)
20-pin
PLCC
(PC20/
PCG20)
112
234
386
4 10 8
5 11 10
6 13 14
7 18 17
8 20 20
44-pin
VQFP
(VQ44)
40
43
13
15
18, 41
21
35
38
44-pin
PLCC
(PC44)
2
5
19
21
24, 3
27
41
44
Capacity
Devices
XC1704L
XC1702L
XC1701/L
XC17512L
XC1736E
XC1765E/EL
XC17128E/EL
XC17256E/EL
Configuration Bits
4,194,304
2,097,152
1,048,576
524,288
36,288
65,536
131,072
262,144
DS027 (v3.5) June 25, 2008
Product Specification
www.xilinx.com
2


Part Number XC1701L
Description Configuration PROMs
Maker Xilinx
Total Page 13 Pages
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