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XC2C64 Datasheet Preview

XC2C64 Datasheet

(XC2C32 - XC2C512) Coolrunner-ii CPLD Family

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0
R CoolRunner-II CPLD Family
DS090 (v3.1) September 11, 2008
0 0 Product Specification
Features
• Optimized for 1.8V systems
- Industry’s fastest low power CPLD
- Densities from 32 to 512 macrocells
• Industry’s best 0.18 micron CMOS CPLD
- Optimized architecture for effective logic synthesis
- Multi-voltage I/O operation — 1.5V to 3.3V
• Advanced system features
- Fastest in system programming
· 1.8V ISP using IEEE 1532 (JTAG) interface
- On-The-Fly Reconfiguration (OTF)
- IEEE1149.1 JTAG Boundary Scan Test
- Optional Schmitt trigger input (per pin)
- Multiple I/O banks on all devices
- Unsurpassed low power management
· DataGATE external signal control
- Flexible clocking modes
· Optional DualEDGE triggered registers
· Clock divider (÷ 2,4,6,8,10,12,14,16)
· CoolCLOCK
- Global signal options with macrocell control
· Multiple global clocks with phase selection per
macrocell
· Multiple global output enables
· Global set/reset
- Abundant product term clocks, output enables and
set/resets
- Efficient control term clocks, output enables and
set/resets for each macrocell and shared across
function blocks
- Advanced design security
- Open-drain output option for Wired-OR and LED
drive
- Optional bus-hold, 3-state or weak pullup on select
I/O pins
- Optional configurable grounds on unused I/Os
- Mixed I/O voltages compatible with 1.5V, 1.8V,
2.5V, and 3.3V logic levels on all parts
- SSTL2_1,SSTL3_1, and HSTL_1 on 128
macrocell and denser devices
- Hot pluggable
• PLA architecture
- Superior pinout retention
- 100% product term routability across function block
• Wide package availability including fine pitch:
- Chip Scale Package (CSP) BGA, Fine Line BGA,
TQFP, PQFP, VQFP, and QFN packages
- Pb-free available for all packages
• Design entry/verification using Xilinx and industry
standard CAE tools
• Free software support for all densities using Xilinx®
WebPACK™ tool
• Industry leading nonvolatile 0.18 micron CMOS
process
- Guaranteed 1,000 program/erase cycles
- Guaranteed 20 year data retention
Family Overview
Xilinx CoolRunner™-II CPLDs deliver the high speed and
ease of use associated with the XC9500/XL/XV CPLD fam-
ily with the extremely low power versatility of the XPLA3
family in a single CPLD. This means that the exact same
parts can be used for high-speed data communications/
computing systems and leading edge portable products,
with the added benefit of In System Programming. Low
power consumption and high-speed operation are com-
bined into a single family that is easy to use and cost effec-
tive. Clocking techniques and other power saving features
extend the users’ power budget. The design features are
supported starting with Xilinx ISE® 4.1i WebPACK tool.
Additional details can be found in Further Reading,
page 14.
Table 1 shows the macrocell capacity and key timing
parameters for the CoolRunner-II CPLD family.
Table 1: CoolRunner-II CPLD Family Parameters
XC2C32A XC2C64A
XC2C128
XC2C256
XC2C384
XC2C512
Macrocells
32 64 128 256 384 512
Max I/O
33 64 100 184 240 270
TPD (ns)
3.8 4.6
5.7
5.7
7.1 7.1
TSU (ns)
1.9 2.0
2.4
2.4
2.9 2.6
TCO (ns)
3.7 3.9
4.2
4.5
5.8 5.8
FSYSTEM1 (MHz)
323
263
244
256
217 179
© 2002–2008 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS090 (v3.1) September 11, 2008
Product Specification
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Xilinx

XC2C64 Datasheet Preview

XC2C64 Datasheet

(XC2C32 - XC2C512) Coolrunner-ii CPLD Family

No Preview Available !

CoolRunner-II CPLD Family
R
Table 2: CoolRunner-II CPLD DC Characteristics
XC2C32A XC2C64A
ICC (μA), 0 MHz, 25°C (typical)
ICC (mA), 50 MHz, 70°C (max)
1. ICC is dynamic current.
16
2.5
17
5
XC2C128
19
10
XC2C256
21
27
XC2C384
23
45
XC2C512
25
55
Table 2 shows key DC characteristics for the CoolRunner-II
family.
Table 3 shows the CoolRunner-II CPLD package offering
with corresponding I/O count. All packages are surface
mount, with over half of them being ball-grid technologies.
The ultra tiny packages permit maximum functional capacity
in the smallest possible area. The CMOS technology used
in CoolRunner-II CPLDs generates minimal heat, allowing
the use of tiny packages during high-speed operation.
With the exception of the Pb-free QF packages, there are at
least two densities present in each package with three in the
VQ100 (100-pin 1.0mm QFP), TQ144 (144-pin 1.4mm
QFP), and FT256 (256-ball 1.0mm spacing FLBGA). The
FT256 is particularly important for slim dimensioned porta-
ble products with mid- to high-density logic requirements.
Table 3: CoolRunner-II CPLD Family Packages and I/O Count
QFG32(1)
XC2C32A
21
XC2C64A
-
XC2C128
-
XC2C256
-
VQ44
VQG44(1)
QFG48(1)
33
33
-
33
33
37
-
-
-
-
-
-
CP56
CPG56(1)
33
33
45
45
-
-
-
-
VQ100
VQG100(1)
-
-
64 80 80
64 80 80
CP132
CPG132(1)
-
-
- 100 106
- 100 106
TQ144
TQG144(1)
-
-
- 100 118
- 100 118
PQ208
-
-
- 173
PQG208(1)
-
-
- 173
FT256 - - - 184
FTG256(1)
-
-
- 184
FG324
-
-
--
FGG324(1)
-
-
-
-
Notes:
1. The letter "G" as the third character indicates a Pb-free package.
XC2C384
-
-
-
-
-
-
-
-
-
-
118
118
173
173
212
212
240
240
XC2C512
-
-
-
-
-
-
-
-
-
-
-
-
173
173
212
212
270
270
Table 4 details the distribution of advanced features across
the CoolRunner-II CPLD family. The family has uniform
basic features with advanced features included in densities
where they are most useful. For example, it is very unlikely
that four I/O banks are needed on 32 and 64 macrocell
parts, but very likely they are for 384 and 512 macrocell
parts. The I/O banks are groupings of I/O pins using any
one of a subset of compatible voltage standards that share
2
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DS090 (v3.1) September 11, 2008
Product Specification


Part Number XC2C64
Description (XC2C32 - XC2C512) Coolrunner-ii CPLD Family
Maker Xilinx
Total Page 16 Pages
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