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XC2S150E-7FG456I Datasheet

Spartan-IIE 1.8V FPGA Family

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R
DS077-1 (v1.0) November 15, 2001
0 Spartan-IIE 1.8V FPGA Family:
Introduction and Ordering
Information
0 0 Preliminary Product Specification
Introduction
The Spartan™-IIE 1.8V Field-Programmable Gate Array
family gives users high performance, abundant logic
resources, and a rich feature set, all at an exceptionally low
price. The five-member family offers densities ranging from
50,000 to 300,000 system gates, as shown in Table 1. Sys-
tem performance is supported beyond 200 MHz.
Spartan-IIE devices deliver more gates, I/Os, and features
per dollar than other FPGAs by combining advanced pro-
cess technology with a streamlined architecture based on
the proven Virtex™-E platform. Features include block RAM
(to 64K bits), distributed RAM (to 98,304 bits), 19 selectable
I/O standards, and four DLLs (Delay-Locked Loops). Fast,
predictable interconnect means that successive design iter-
ations continue to meet timing requirements.
The Spartan-IIE family is a superior alternative to
mask-programmed ASICs. The FPGA avoids the initial cost,
lengthy development cycles, and inherent risk of
conventional ASICs. Also, FPGA programmability permits
design upgrades in the field with no hardware replacement
necessary (impossible with ASICs).
Features
• Second generation ASIC replacement technology
- Densities as high as 6,912 logic cells with up to
300,000 system gates
- Streamlined features based on Virtex-E
architecture
- Unlimited in-system reprogrammability
- Very low cost
• System level features
- SelectRAM+™ hierarchical memory:
· 16 bits/LUT distributed RAM
· Configurable 4K-bit true dual-port block RAM
· Fast interfaces to external RAM
- Fully 3.3V PCI compliant to 64 bits at 66 MHz and
CardBus compliant
- Low-power segmented routing architecture
- Full readback ability for verification/observability
- Dedicated carry logic for high-speed arithmetic
- Efficient multiplier support
- Cascade chain for wide-input functions
- Abundant registers/latches with enable, set, reset
- Four dedicated DLLs for advanced clock control
- Four primary low-skew global clock distribution nets
- IEEE 1149.1 compatible boundary scan logic
Versatile I/O and packaging
- Low cost packages available in all densities
- Family footprint compatibility in common packages
- 19 high-performance interface standards, including
LVDS and LVPECL
- Up to 120 differential I/O pairs that can be input,
output, or bidirectional
- Zero hold time simplifies system timing
Fully supported by powerful Xilinx ISE development
system
- Fully automatic mapping, placement, and routing
- Integrated with design entry and verification tools
Table 1: Spartan-IIE FPGA Family Members
Device
Logic
Cells
Typical
System Gate Range
(Logic and RAM)
XC2S50E 1,728
23,000 - 50,000
XC2S100E 2,700 37,000 - 100,000
XC2S150E 3,888 52,000 - 150,000
XC2S200E 5,292 71,000 - 200,000
XC2S300E 6,912 93,000 - 300,000
CLB
Array
(R x C)
16 x 24
20 x 30
24 x 36
28 x 42
32 x 48
Total
CLBs
384
600
864
1,176
1,536
Maximum
Available
User I/O
182
202
263
289
329
Maximum
Differential
I/O Pairs
84
86
114
120
120
Distributed Block
RAM Bits RAM Bits
24,576
32K
38,400
40K
55,296
48K
75,264
56K
98,304
64K
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS077-1 (v1.0) November 15, 2001
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
1




Xilinx

XC2S150E-7FG456I Datasheet Preview

XC2S150E-7FG456I Datasheet

Spartan-IIE 1.8V FPGA Family

No Preview Available !

Spartan-IIE 1.8V FPGA Family: Introduction and Ordering Information
R
General Overview
The Spartan-IIE family of FPGAs have a regular, flexible,
programmable architecture of Configurable Logic Blocks
(CLBs), surrounded by a perimeter of programmable
Input/Output Blocks (IOBs). There are four Delay-Locked
Loops (DLLs), one at each corner of the die. Two columns
of block RAM lie on opposite sides of the die, between the
CLBs and the IOB columns. These functional elements are
interconnected by a powerful hierarchy of versatile routing
channels (see Figure 1).
Spartan-IIE FPGAs are customized by loading configura-
tion data into internal static memory cells. Unlimited repro-
gramming cycles are possible with this approach. Stored
values in these cells determine logic functions and intercon-
nections implemented in the FPGA. Configuration data can
be read from an external serial PROM (master serial mode),
or written into the FPGA in slave serial, slave parallel, or
Boundary Scan modes. The Xilinx XC17S00A PROM family
is recommended for serial configuration of Spartan-IIE
FPGAs. The XC18V00 reprogrammable PROM family is
recommended for parallel or serial configuration.
Spartan-IIE FPGAs are typically used in high-volume appli-
cations where the versatility of a fast programmable solution
adds benefits. Spartan-IIE FPGAs are ideal for shortening
product development cycles while offering a cost-effective
solution for high volume production.
Spartan-IIE FPGAs achieve high-performance, low-cost
operation through advanced architecture and semiconduc-
tor technology. Spartan-IIE devices provide system clock
rates beyond 200 MHz. Spartan-IIE FPGAs offer the most
cost-effective solution while maintaining leading edge per-
formance. In addition to the conventional benefits of
high-volume programmable logic solutions, Spartan-IIE
FPGAs also offer on-chip synchronous single-port and
dual-port RAM (block and distributed form), DLL clock driv-
ers, programmable set and reset on all flip-flops, fast carry
logic, and many other features.
Spartan-IIE Family Compared to Spartan-II
Family
Higher density and more I/O
Higher performance
Unique pinouts in cost-effective packages
Differential signaling
- LVDS, Bus LVDS, LVPECL
VCCINT = 1.8V
- Lower power
- 5V tolerance with 100external resistor
- 3V tolerance directly
PCI, LVTTL, and LVCMOS2 input buffers powered by
VCCO instead of VCCINT
Unique larger bitstream
DLL DLL
DLL DLL
I/O LOGIC
DS077_01_102201
Figure 1: Basic Spartan-IIE Family FPGA Block Diagram
2
www.xilinx.com
DS077-1 (v1.0) November 15, 2001
1-800-255-7778
Preliminary Product Specification


Part Number XC2S150E-7FG456I
Description Spartan-IIE 1.8V FPGA Family
Maker Xilinx
Total Page 4 Pages
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