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XC2VP50 Datasheet Preview

XC2VP50 Datasheet

(XC2VPxxx) Platform Flash In-System Programmable Configuration PROMS

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R
DS123 (v2.9) May 09, 2006
0
Features
In-System Programmable PROMs for Configuration of
Xilinx FPGAs
Low-Power Advanced CMOS NOR FLASH Process
Endurance of 20,000 Program/Erase Cycles
Operation over Full Industrial Temperature Range
(–40°C to +85°C)
IEEE Standard 1149.1/1532 Boundary-Scan (JTAG)
Support for Programming, Prototyping, and Testing
JTAG Command Initiation of Standard FPGA
Configuration
Cascadable for Storing Longer or Multiple Bitstreams
Dedicated Boundary-Scan (JTAG) I/O Power Supply
(VCCJ)
I/O Pins Compatible with Voltage Levels Ranging From
1.5V to 3.3V
Design Support Using the Xilinx Alliance ISE and
Foundation ISE Series Software Packages
Platform Flash In-System
Programmable Configuration
PROMS
Product Specification
XCF01S/XCF02S/XCF04S
3.3V supply voltage
Serial FPGA configuration interface (up to 33 MHz)
Available in small-footprint VO20 and VOG20
packages.
XCF08P/XCF16P/XCF32P
1.8V supply voltage
Serial or parallel FPGA configuration interface
(up to 33 MHz)
Available in small-footprint VO48, VOG48, FS48,
and FSG48 packages
Design revision technology enables storing and
accessing multiple design revisions for
configuration
Built-in data decompressor compatible with Xilinx
advanced compression technology
Table 1: Platform Flash PROM Features
Device Density VCCINT VCCO Range VCCJ Range
Packages
XCF01S
XCF02S
XCF04S
XCF08P
1 Mbit
2 Mbit
4 Mbit
8 Mbit
XCF16P 16 Mbit
XCF32P 32 Mbit
3.3V
3.3V
3.3V
1.8V
1.8V
1.8V
1.8V – 3.3V 2.5V – 3.3V
1.8V – 3.3V 2.5V – 3.3V
1.8V – 3.3V 2.5V – 3.3V
1.5V – 3.3V 2.5V – 3.3V
1.5V – 3.3V 2.5V – 3.3V
1.5V – 3.3V 2.5V – 3.3V
VO20/VOG20
VO20/VOG20
VO20/VOG20
VO48/VOG48
FS48/FSG48
VO48/VOG48
FS48/FSG48
VO48/VOG48
FS48/FSG48
Program
In-system
via JTAG
Serial
Config.
Parallel
Config.
Design
Revisioning
Compression
✓ ✓✓ ✓
✓ ✓✓ ✓
✓ ✓✓ ✓
Description
Xilinx introduces the Platform Flash series of in-system
programmable configuration PROMs. Available in 1 to 32
Megabit (Mbit) densities, these PROMs provide an
easy-to-use, cost-effective, and reprogrammable method
for storing large Xilinx FPGA configuration bitstreams. The
Platform Flash PROM series includes both the 3.3V
XCFxxS PROM and the 1.8V XCFxxP PROM. The XCFxxS
version includes 4-Mbit, 2-Mbit, and 1-Mbit PROMs that
support Master Serial and Slave Serial FPGA configuration
modes (Figure 1, page 2). The XCFxxP version includes
32-Mbit, 16-Mbit, and 8-Mbit PROMs that support Master
Serial, Slave Serial, Master SelectMAP, and Slave
SelectMAP FPGA configuration modes (Figure 2, page 2).
A summary of the Platform Flash PROM family members
and supported features is shown in Table 1.
© 2003-2006 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
PowerPC is a trademark of IBM, Inc. All other trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS123 (v2.9) May 09, 2006
www.xilinx.com
1



Xilinx
Xilinx

XC2VP50 Datasheet Preview

XC2VP50 Datasheet

(XC2VPxxx) Platform Flash In-System Programmable Configuration PROMS

No Preview Available !

XC2VP50 pdf
R Platform Flash In-System Programmable Configuration PROMS
CLK CE
OE/RESET
TCK
TMS
TDI
Control
and
JTAG
Interface
Data
Address
Memory
Data
Serial
Interface
TDO
CEO
DATA (D0)
Serial Mode
CF
Figure 1: XCFxxS Platform Flash PROM Block Diagram
ds123_01_30603
FI
CLK CE
EN_EXT_SEL
OE/RESET BUSY
OSC
TCK
TMS
TDI
TDO
Control
and
JTAG
Interface
Data
Address
Memory
Data
Decompressor
Serial
or
Parallel
Interface
CLKOUT
CEO
DATA (D0)
(Serial/Parallel Mode)
D[1:7]
(Parallel Mode)
CF REV_SEL [1:0]
Figure 2: XCFxxP Platform Flash PROM Block Diagram
ds123_19_122105
When the FPGA is in Master Serial mode, it generates a
configuration clock that drives the PROM. With CF High, a
short access time after CE and OE are enabled, data is
available on the PROM DATA (D0) pin that is connected to
the FPGA DIN pin. New data is available a short access
time after each rising clock edge. The FPGA generates the
appropriate number of clock pulses to complete the
configuration.
When the FPGA is in Slave Serial mode, the PROM and the
FPGA are both clocked by an external clock source, or
optionally, for the XCFxxP PROM only, the PROM can be
used to drive the FPGA’s configuration clock.
The XCFxxP version of the Platform Flash PROM also
supports Master SelectMAP and Slave SelectMAP (or
Slave Parallel) FPGA configuration modes. When the FPGA
is in Master SelectMAP mode, the FPGA generates a
configuration clock that drives the PROM. When the FPGA
is in Slave SelectMAP Mode, either an external oscillator
generates the configuration clock that drives the PROM and
the FPGA, or optionally, the XCFxxP PROM can be used to
drive the FPGA’s configuration clock. With BUSY Low and
CF High, after CE and OE are enabled, data is available on
the PROMs DATA (D0-D7) pins. New data is available a
short access time after each rising clock edge. The data is
clocked into the FPGA on the following rising edge of the
CCLK. A free-running oscillator can be used in the Slave
Parallel /Slave SelecMAP mode.
The XCFxxP version of the Platform Flash PROM provides
additional advanced features. A built-in data decompressor
supports utilizing compressed PROM files, and design
revisioning allows multiple design revisions to be stored on
a single PROM or stored across several PROMs. For design
revisioning, external pins or internal control bits are used to
select the active design revision.
Multiple Platform Flash PROM devices can be cascaded to
support the larger configuration files required when
targeting larger FPGA devices or targeting multiple FPGAs
daisy chained together. When utilizing the advanced
features for the XCFxxP Platform Flash PROM, such as
design revisioning, programming files which span cascaded
PROM devices can only be created for cascaded chains
containing only XCFxxP PROMs. If the advanced XCFxxP
features are not enabled, then the cascaded chain can
include both XCFxxP and XCFxxS PROMs.
DS123 (v2.9) May 09, 2006
www.xilinx.com
2


Part Number XC2VP50
Description (XC2VPxxx) Platform Flash In-System Programmable Configuration PROMS
Maker Xilinx
Total Page 30 Pages
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