XC3SD3400A Description
DS610 (v3.0) October 4, 2010 The functionality of the Spartan®-3A DSP FPGA family is described in the following documents. Spartan-3 Generation FPGA User Guide Clocking Resources Digital Clock Managers (DCMs) Block RAM Configurable Logic Blocks (CLBs) - Distributed RAM - SRL16 Shift Registers - Carry and Arithmetic Logic I/O Resources Programmable Interconnect ISE® Software Design Tools and IP Cores Embedded...
XC3SD3400A Key Features
- Architectural Overview
- Configuration Overview
- General I/O Capabilities
- Supported Packages and Package Marking
- Ordering Information
- UG331: Spartan-3 Generation FPGA User Guide
- Clocking Resources
- Digital Clock Managers (DCMs)
- Block RAM
- Configurable Logic Blocks (CLBs)