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Z-Communications

PSN1810A-LF Datasheet Preview

PSN1810A-LF Datasheet

Satellite Communication

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9939 Via Pasar • San Diego, CA 92126
TEL (858) 621-2700 FAX (858) 621-2722
PSN1810A-LF
PHASE LOCKED LOOP
Rev A1
PHASE NOISE (1 Hz BW, typical)
-40
-60
-100
FEATURES
• Frequency Range: 1780 - 1840 MHz
• Step Size:
50 KHz
PLL - Style Package
APPLICATIONS
• Fixed Wireless
• Satellite Communications
-140
-180
-220
100 Hz
1 kHz
10 kHz 100 kHz
PERFORMANCE SPECIFICATIONS
Frequency Range
VALUE
1780 - 1840
Phase Noise @ 10 kHz offset (1 Hz BW, typ.)
-101
Harmonic Suppression (2nd, typ.)
Sideband Spurs (typ.)
-15
-65
Power Output
4±2
Load Impedance
Step Size
50
50
Charge Pump Output Current
1000
Switching Speed (typ., adjacent channel)
Startup Lock Time (typ.)
Operating Temperature Range
5
10
-40 to 85
Package Style
PLL
POWER SUPPLY REQUIREMENTS
Supply Voltage (Vcc, nom.)
5
Supply Current (Icc, typ.)
34
All specifications are typical unless otherwise noted and subject to change without notice.
UNITS
MHz
dBc/Hz
dBc
dBc
dBm
KHz
mSec
mSec
°C
Vdc
mA
APPLICATION NOTES
wwAwN.D-1a0ta7Sh:eeHt4oUw.cotmo Solder Z-COMM VCOs / PLLs
AN-200 : Mounting and Grounding of Z-COMM PLLs
AN-201 : PLL Fundamentals
AN-202 : PLL Functional Description
NOTES:
Reference Oscillator Signal: 5 MHz< <40 MHz
Frequency Synthesizer: National Semiconductor - LMX2326
© Z-Communications, Inc.
Page 1
All rights reserved




Z-Communications

PSN1810A-LF Datasheet Preview

PSN1810A-LF Datasheet

Satellite Communication

No Preview Available !

LOW COST - HIGH PERFORMANCE
PHASE LOCKED LOOP
1890
1870
1850
1830
1810
1790
1770
1750
1730
1710
1690
1670
0 0.5 1
8
7
6
5
4
3
2
1
0
1697
1723
1746
VCO TUNING CURVE, typ.
1.5 2 2.5
TUNING VOLTAGE (Vdc)
VCO POWER CURVE, typ.
3
1768
1790
1812
FREQUENCY (MHz)
1834
PHYSICAL DIMENSIONS
PLL
415-0078 REV. F
(DRAWING NOT TO SCALE)
0.000 -0.025
0.148
0.321
0.495
BOTTOM
SEE DETAIL A
0.668
0.841 0.816
www.DataSheet4U.com
SEE DETAIL B
14 13 12
0.140
1 11
2 10
39
48
56 7
P1 RF OUTPUT
P2 GROUND
.032
P3 REFERENCE OSCILLATOR INPUT
P4 CLOCK
P5 DATA
P6 LOAD ENABLE
P7 LOCK DETECT
P8 VCC
P9 OPTIONAL
P10 NO CONNECTION
P11-14 GROUND
DETAIL A
TABS RANGE:
SEE NOTE 5.
(4 PLACES)
.070
.015
.030
DETAIL B (TYP)
PSN1810A-LF
PAGE 2
85 °c
25 °c
-40 °c
3.5 4
85 °c
25 °c
-40 °c
1855
1876
NOTES:
1. THE INSIDE RADIUS OF ALL 14 HALF HOLES
AT THE PERIMETER OF THE BOARD ARE
PLATED TO PROVIDE A SURFACE FOR THE
ATTACHMENT OF THE PLL MODULE TO A PCB,
IN 11 LOCATIONS, WITH 3 PADS BEING
USED FOR ELECTROMECHANICAL INTERFACE.
14 SOLDER LOCATIONS REQUIRED.
2. THE SURFACE OF THE SHIELD IS TIN PLATED
AND MAY BE SOLDERED TO. THE SHIELD'S
BASE METAL IS COLD ROLLED STEEL.
3. THE GROUND PLANE IS GROUND AND ATTACHES
TO A GROUND TRACK ON THE UPPER SIDE OF
THE BOARD AS WELL AS THE SHIELD BY PTH.
4. UNLESS OTHERWISE NOTED ALL DIMENSIONS
ARE IN INCHES.
5. UNLESS OTHERWISE NOTED ALL TOLERANCES
ARE AS FOLLOWS:
TOLERANCES
.XXX= ± .010
© Z-Communications, Inc.
Page 2
Printed in the U.S.A.


Part Number PSN1810A-LF
Description Satellite Communication
Maker Z-Communications
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