1 18 GNDD
2 17 VRef
3 16 GNDA
4 15 VR
5 14 ANUL
6 13 VX
7 12 VEE
8 11 SD0
9 10 SD1
18 PIN PDIP
20 PIN PDIP/SOIC
Figure 2 - Pin Connections
Control ST-BUS In is a TTL-compatible digital input used to control the function of the filter/codec.
Three modes of operation may be effected by applying to this input a logic high (VDD), logic low
(GNDD), or an 8-bit serial word, depending on the logic states of CA and F1i.
Functions controlled are: powerdown, filter gain adjust, loopback, chip testing, SD outputs.
Data ST-BUS In accepts the incoming 8-bit PCM word. Input is TTL-compatible.
Clock Input is a TTL-compatible 2.048 MHz clock.
Data ST-BUS Out is a three-state digital output driving the PCM bus with the outgoing 8-bit PCM
Positive power Supply (+5 V).
Synchronization Input is an active low digital input enabling (in conjunction with CA) the PCM input,
PCM output and digital control input. It is internally sampled on every positive edge of the clock, C2i,
and provides frame and channel synchronization.
Control Address is a three-level digital input which enables PCM input and output and determines
into which control register (A or B) the serial data, presented to CSTi, is stored.
System Drive Output is an open drain output of an N-channel transistor which has its source tied to
GNDA. Inactive state is open circuit.
System Drive Outputs are open drain outputs of N-channel transistors which have their source tied
to GNDD. Inactive state is open circuit.
System Drive Outputs are “Totempole“ CMOS outputs switching between GNDD and VDD. Inactive
state is logic low.
Negative power supply (-5 V).
Voice Transmit is the analog input to the transmit filter.
Auto Null is used to integrate an internal auto-null signal. A 0.1 µF capacitor must be connected
between this pin and GNDA.
Voice Receive is the analog output of the receive filter.
Analog ground (0 V).
Voltage Reference input to D to A converter.
Digital ground (0 V).
Zarlink Semiconductor Inc.