PDSP16116 Datasheet | Zarlink Semiconductor

.. PDSP16116/A/MC 16 by 16 Bit plex Multiplier PDSP16116/A/MC DS3858 ISSUE 3.0 June 2000 The PDSP16116A will multiply two plex (16 + 16) bit words every 50ns and can be configured to output the plete plex (32 + 32) bit result within a single cycle. The data format is fractional two's plement. The PDSP16116/A contains four 16 x 16 Array Multipliers, two 32 bit Adder/Subtractors and all the control logic required to support Block Floating Point Arithmetic as used in FFT applications. In bination with a PDSP16318, the PDSP16116A forms a two chip 10MHz plex Multiplier Accumulator with 20 bit accumulator registers and output shifters. The PDSP16116 in...