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PDSP16116A - 16 by 16 Bit Complex Multiplier

Download the PDSP16116A datasheet PDF. This datasheet also covers the PDSP16116 variant, as both devices belong to the same 16 by 16 bit complex multiplier family and are provided as variant models within a single manufacturer datasheet.

Description

16 bit input for real x data 16 bit input for imag x data 16 bit input for reaal y data 16 bit input for imag y data 16 bit output for real p data 16 bit output for img p data Clock, new data is loaded on rising edge of CLK Clock, enable X-port input register Clock, enable Y-port input register Conj

Features

  • s s s s s s s s s s Complex Number (16 + 16) X (16 + 16) Multiplication Full 32 bit Result 20MHz Clock Rate Block Floating Point FFT Butterfly Support -1 times -1 Trap Two's Complement Fractional Arithmetic TTL Compatible I/O Complex Conjugation 2 Cycle Fall Through 144 pin PGA or QFP packages MULT MULT MULT MULT REG REG REG REG.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (PDSP16116_ZarlinkSemiconductor.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number PDSP16116A
Manufacturer Zarlink Semiconductor
File Size 174.85 KB
Description 16 by 16 Bit Complex Multiplier
Datasheet download datasheet PDSP16116A Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
PDSP16116AA0AC 16 X 16 Bit Complex Multiplier Mitel Networks Corporation
PDSP16116AB0AC 16 X 16 Bit Complex Multiplier Mitel Networks Corporation
PDSP16116AB0GG 16 X 16 Bit Complex Multiplier Mitel Networks Corporation
PDSP16116AMCGGDR 16 X 16 Bit Complex Multiplier Mitel Networks Corporation
PDSP16116 16 X 16 Bit Complex Multiplier Mitel Networks Corporation

Other Datasheets by Zarlink Semiconductor

Part Number Description
PDSP16116 16 by 16 Bit Complex Multiplier
PDSP16116MC 16 by 16 Bit Complex Multiplier
PDSP16112 16 X 12 BIT COMPLEX MULTIPLIER
PDSP16112A 16 X 12 BIT COMPLEX MULTIPLIER
PDSP1601 ALU and Barrel Shifter

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
www.DataSheet4U.com PDSP16116/A/MC 16 by 16 Bit Complex Multiplier PDSP16116/A/MC DS3858 ISSUE 3.0 June 2000 The PDSP16116A will multiply two complex (16 + 16) bit words every 50ns and can be configured to output the complete complex (32 + 32) bit result within a single cycle. The data format is fractional two's complement. The PDSP16116/A contains four 16 x 16 Array Multipliers, two 32 bit Adder/Subtractors and all the control logic required to support Block Floating Point Arithmetic as used in FFT applications. In combination with a PDSP16318, the PDSP16116A forms a two chip 10MHz Complex Multiplier Accumulator with 20 bit accumulator registers and output shifters.
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