WL102B Datasheet | Zarlink Semiconductor

Features - - - - - - - - plete CMOS, single chip, radio transceiver controller Hardware implemented munication Control Block (CCB) Protocol independent design using external flash memory Internal 8051 and external processor options Internal/external buffer and processor RAM Block power down facility PCMCIA/8bit processor host interface to buffer RAM Up to 1Mbps/2 level or 2 Mbps/4 level operation Ordering Information WL102B/IG/TP1N 100 pin package WL102BC/PR/FP1R 144 pin package The WL102B is a highly integrated CMOS wireless data controller designed to dramatically reduce the cost of radio data applications. It works with the WL600C RF IF chip and WL800 synthesiser chip to offer a plete solution for a frequency hopping, spread spectrum radio in the 2.4 to 2.45GHz ISM band. Its flexible design means that it can also be used in a wide range of other applications using a range of "processor", protocols and additional memory options as well as radios at other frequencies. Related Documents WL600 (DS4581), WL800 (DS5241) and WL102B (DS4837) Datasheets Receive Transmit DMA Status Control munications Control Block Memory Control Block Buffer RAM 6K4 Interrupt Address Data Control Address Data Control Port Pins Interrupt 8051 System RAM 4K Counters Power Down Control Attribute Memory WL102 Configuration Figure 1 - WL102 Minimum configuration block diagram SP102 Advance Information HD1 HD0 HA1 HREGB HA2 HA3 HWAITB HA4 HRESET HA5 HA6 HA7 HRDY HWEB HA0 HWRB HRDB HVdd HGnd HOEB HCEB HD7 HD6 HD5 HD4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 HD3 SA11 SA9 SA8 SA13 SVdd SGnd SA14 SWRB SA15 SA12 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 SD0 SD1 SVdd SGnd P3[0] / EPSYSINC EPRSTB 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 SYSCLK SYSCLK_GND AGnd AVdd RXD_L RXD_LB RXD_H RXD_HB THREEV SWAKEUP / EPTCNT2 EPRDYB ENIBRAMB CCAB SRDB SPSENB SA10 CCEB SD7...