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* Single chip low cost solution for synchronizing an Ethernet PHY to a standard telecom clock Generates an IEEE 802.3 jitter compliant 25 MHz Gigabit Ethe.

* Ethernet Line Cards Supporting Synchronous Transmission X1/CLK X2 LOCK REF0 REF1 REF2 DPLL APLL CLK uP I/F .

Pin # B1 A3 B4 D8 G5 Name REF0 REF1 REF2 CLK RST I/O Type Id Description Shortform Data Sheet Reference Inputs (LVCMOS, Schmitt Trigger). These reference inputs are used for synchronizing the PLL. These pins are internally pulled down to Vss. SONET.

ZL30100

ZL30101

ZL30102

ZL30105

ZL30106

ZL30108

ZL30109

ZL30110

ZL30111

ZL30112

ZL30116

ZL30117

ZL30119