ZL50073 Datasheet | Zarlink Semiconductor

Features - 32,768 channel x 32,768 channel non-blocking digital Time Division Multiplex (TDM) switch at 65.536 Mbps, 32.768 Mbps and 16.384 Mbps or using a bination of rates 16,384 channel x 16,384 channel non-blocking digital TDM switch at 8.192 Mbps High jitter tolerance with multiple input clock sources and frequencies Up to 128 serial TDM input streams, divided into 32 groups with 4 input streams per group Up to 128 serial TDM output streams, divided into 32 groups with 4 output streams per group Per-group input and output data rate conversion selection at 65.536 Mbps, 32.768 Mbps, 16.384 Mbps and 8.192 Mbps. Input and output data group rates can differ Per-group input bit delay for flexible sampling point selection Per-group output fractional bit advancement Four sets of output timing signals for interfacing additional devices Per-channel A-Law/µ-Law Translation - - - - - - Ordering Information ZL50073GAC 484 Ball PBGA - - - - - -40° C to +85 ° C Per-channel constant or variable throughput delay for frame integrity and low latency applications Per-stream Bit Error Rate (BER) test circuits Per-channel high impedance output control Per-channel force high output control Per-channel message mode Control interface patible with Intel and Motorola Selectable 32 bit and 16 bit nonmultiplexed buses Connection Memory block programming Supports ST-BUS and GCI-Bus standards for input and output timing IEEE 1149.1 (JTAG) test port 3.3 V I/O with 5 V tolerant inputs; 1.8 V core voltage ODE PWR - - - - - - - - VDD_CORE VDD_IO Input Group 0 STi A0 STi B0 STi C0 STi D0 Output Group 0 Data Memory S/P Converter Connection Memory P/S Converter Input Group 31 : : STo A0 STo B0 STo C0 STo D0 STi A31 STi B31 STi C31 STi D31 Input Timing STo A31 STo B31 STo C31 STo D31 Output Timing : : Output Group 31 FPi2-0 CKi2-0 CK_SEL1-0 FPo3-0 CKo3-0 Timing Microprocessor Interface and Control Registers Test Access Port A18-0 DTA WAIT BERR D31-0 TMS TDi TDo TCK Figure 1 - ZL50073...