* - VDD=VDDQ=2.5V+0.2V (-50) - Double data rate architecture ; two data transfers per clock cycle. - Bidirectional , data strobe (DQS) is transmitted/received with data - Differential clock input (CLK and /CLK) - DLL aligns DQ and DQS transitions with CLK transitions edges of DQS - Commands entered on
A3S28D40JTP Datasheet (533.07 KB)
A3S28D40JTP
Zentel
533.07 KB
128m double data rate synchronous dram.
A3S28D40JTP 128M Double Data Rate Synchronous DRAM 128Mb DDR SDRAM Specification A3S28D40JTP Zentel Electronics Corp. Revision 1.0 Oct., 2013 A3S2.
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