- VDD=VDDQ=2.5V+0.2V (-50) - Double data rate architecture ; two data transfers per clock cycle. - Bidirectional , data strobe (DQS) is transmitted/received with data - D.

A3S28D40JTP is a 4-bank x 2,097,152-word x 16bit double data rate synchronous DRAM , with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK. Input data is registered on both edges of data strobe ,and output da.

A3S28D40FTP

A3S28D30FTP

A3S12D30ETP

A3S12D40ETP

A3S56D30ETP

A3S56D30FTP

A3S56D30GTP

A3S56D40ETP

A3S56D40FTP

A3S56D40GTP

A3S64D40GTP

A3-44PA-2SV

A3-xxxA-2xx