This document provides electrical specifications, pin assignments, and package diagrams for the
PC5566 microcontroller device. For functional characteristics, refer to the MPC5566 Microcontroller
Reference Manual from Freescale. Other Freescale documents related to MPC5566 apply.
The PC5566 microcontroller (MCU) is a member of the MPC5500 family of microcontrollers built on the
Power Architecture® embedded technology. This family of parts has many new features coupled with
high performance CMOS technology to provide substantial reduction of cost per feature and significant
performance improvement over the MPC500 family.
The host processor core of this device complies with the Power Architecture embedded category that is
100% user-mode compatible (including floating point library) with the original PowerPC instruction
set.The embedded architecture enhancements improve the performance in embedded applications. The
core also has additional instructions, including digital signal processing (DSP) instructions, beyond the
original PowerPC instruction set.
The MPC5500 family of parts contains many new features coupled with high performance CMOS
technology to provide significant performance improvement over the MPC565x.
The host processor core of the PC5566 also includes an instruction set enhancement allowing variable
length encoding (VLE). This allows optional encoding of mixed 16- and 32-bit instructions. With this
enhancement, it is possible to significantly reduce the code size footprint.
The PC5566 has two levels of memory hierarchy. The fastest accesses are to the 32-kilobytes (KB)
unified cache. The next level in the hierarchy contains the 128-KB on-chip internal SRAM and three-
megabytes (MB) internal flash memory. The internal SRAM and flash memory hold instructions and
data. The external bus interface is designed to support most of the standard memories used with the
The complex input/output timer functions of the PC5566 are performed by two enhanced time processor
unit (eTPU) engines. Each eTPU engine controls 32 hardware channels, providing a total of 64 hardware
channels. The eTPU has been enhanced over the TPU by providing: 24-bit timers, double-action
hardware channels, variable number of parameters per channel, angle clock hardware, and additional
control and arithmetic instructions. The eTPU is programmed using a high-level programming language.
e2v semiconductors SAS 2014
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