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PC5566 Datasheet Preview

PC5566 Datasheet

Microcontroller

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PC5566 pdf
Datasheet
PC5566
Microcontroller
This document provides electrical specifications, pin assignments, and package diagrams for the
PC5566 microcontroller device. For functional characteristics, refer to the MPC5566 Microcontroller
Reference Manual from Freescale. Other Freescale documents related to MPC5566 apply.
1. Overview
The PC5566 microcontroller (MCU) is a member of the MPC5500 family of microcontrollers built on the
Power Architecture® embedded technology. This family of parts has many new features coupled with
high performance CMOS technology to provide substantial reduction of cost per feature and significant
performance improvement over the MPC500 family.
The host processor core of this device complies with the Power Architecture embedded category that is
100% user-mode compatible (including floating point library) with the original PowerPC instruction
set.The embedded architecture enhancements improve the performance in embedded applications. The
core also has additional instructions, including digital signal processing (DSP) instructions, beyond the
original PowerPC instruction set.
The MPC5500 family of parts contains many new features coupled with high performance CMOS
technology to provide significant performance improvement over the MPC565x.
The host processor core of the PC5566 also includes an instruction set enhancement allowing variable
length encoding (VLE). This allows optional encoding of mixed 16- and 32-bit instructions. With this
enhancement, it is possible to significantly reduce the code size footprint.
The PC5566 has two levels of memory hierarchy. The fastest accesses are to the 32-kilobytes (KB)
unified cache. The next level in the hierarchy contains the 128-KB on-chip internal SRAM and three-
megabytes (MB) internal flash memory. The internal SRAM and flash memory hold instructions and
data. The external bus interface is designed to support most of the standard memories used with the
MPC5xx family.
The complex input/output timer functions of the PC5566 are performed by two enhanced time processor
unit (eTPU) engines. Each eTPU engine controls 32 hardware channels, providing a total of 64 hardware
channels. The eTPU has been enhanced over the TPU by providing: 24-bit timers, double-action
hardware channels, variable number of parameters per channel, angle clock hardware, and additional
control and arithmetic instructions. The eTPU is programmed using a high-level programming language.
e2v semiconductors SAS 2014
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1120B–BDC–05/14



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PC5566 Datasheet Preview

PC5566 Datasheet

Microcontroller

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PC5566 pdf
PC5566
The less complex timer functions of the PC5566 are performed by the enhanced modular input/output
system (eMIOS). The eMIOS’ 24 hardware channels are capable of single-action, double-action, pulse-
width modulation (PWM), and modulus-counter operations. Motor control capabilities include edge-
aligned and center-aligned PWM.
Off-chip communication is performed by a suite of serial protocols including controller area networks
(FlexCANs), enhanced deserial/serial peripheral interfaces (DSPIs), and enhanced serial
communications interfaces (eSCIs). The DSPIs support pin reduction through hardware serialization and
deserialization of timer channels and general-purpose input/output (GPIOs) signals.
The MCU has an on-chip enhanced queued dual analog-to-digital converter (eQADC).s 40-channels.
The system integration unit (SIU) performs several chip-wide configuration functions. Pad configuration
and general-purpose input and output (GPIO) are controlled from the SIU. External interrupts and reset
control are also determined by the SIU. The internal multiplexer submodule provides multiplexing of
eQADC trigger sources, daisy chaining the DSPIs, and external interrupt signal multiplexing.
The Fast Ethernet (FEC) module is a RISC-based controller that supports both 10 and 100 Mbps
Ethernet/IEEE® 802.3 networks and is compatible with three different standard MAC (media access
controller) PHY (physical) interfaces to connect to an external Ethernet bus. The FEC supports the 10 or
100 Mbps MII (media independent interface), and the 10 Mbps-only with a seven-wire interface, which
uses a subset of the MII signals. The upper 16-bits of the 32-bit external bus interface (EBI) are used to
connect to an external Ethernet device. The FEC contains built-in transmit and receive message FIFOs
and DMA support.
2. Electrical Characteristics
This section contains detailed information on power considerations, DC/AC electrical characteristics,
and AC timing specifications for the MCU.
2
1120B–BDC–05/14
e2v semiconductors SAS 2014


Part Number PC5566
Description Microcontroller
Maker e2v
Total Page 30 Pages
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