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PC8240 Datasheet Preview

PC8240 Datasheet

Integrated Processor

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PC8240
Integrated Processor Family
Datasheet - Preliminary Specification
Features
6.6 SPEC int 95, 5.5 SPECfp95 at 266 MHz (Estimated)
Superscalar 603e Core
Integer Unit (IU), Floating-Point Unit (FPU) (User Enabled or Disabled), Load/Store Unit (LSU), System Register Unit (SRU),
and a Branch Processing Unit (BPU)
16-Kbyte Instruction Cache
16-Kbyte Data Cache
Lockable L1 Caches - Entire Cache or on a Per-way Basis up to 3 of 4 Ways
Dynamic Power Management
High-bandwidth Bus (32/64 bits Data Bus) to DRAM
Supports 1-Mbyte to 1-Gbyte DRAM Memory
32-bit PCI Interface Operating up to 66 MHz
PCI 2.1-compliant, 5.0V Tolerance
Fint Max = 200 MHz
FBus Max = 66 MHz
Description
The PC8240 combines a Power Architecture603e core microprocessor with a PCI bridge. The PC8240’s PCI support will
allow system designers to rapidly design systems using peripherals already designed for PCI and the other standard inter-
faces. The PC8240 also integrates a highperformance memory controller which supports various types of DRAM and
ROM. The PC8240 is the first of a family of products that provides system level support for industry standard interfaces with
a Power Architecture microprocessor core.
The peripheral logic integrates a PCI bridge, memory controller, DMA controller, EPIC interrupt controller, I2O controller,
and a two-wire interface controller. The 603e core is a full-featured, high-performance processor with floating-point support,
memory management, 16-Kbyte instruction cache, 16-Kbyte data cache, and power management features. The integration
reduces the overall packaging requirements and the number of discrete devices required for an embedded system.
The PC8240 contains an internal peripheral logic bus that interfaces the 603e core to the peripheral logic. The core can
operate at a variety of frequencies, allowing the designer to trade off performance for power consumption. The 603e core is
clocked from a separate PLL, which is referenced to the peripheral logic PLL. This allows the microprocessor and the
peripheral logic block to operate at different frequencies, while maintaining a synchronous bus interface. The interface uses
a 64- or 32-bit data bus (depending on memory data bus width) and a 32-bit address bus along with control signals that
enable the interface between the processor and peripheral logic to be optimized for performance. PCI accesses to the
PC8240’s memory space are passed to the processor bus for snooping purposes when snoop mode is enabled.
e2v semiconductors SAS 2009
Visit our website: www.e2v.com
for the latest version of the datasheet
0885C–HIREL–02/09




e2v

PC8240 Datasheet Preview

PC8240 Datasheet

Integrated Processor

No Preview Available !

PC8240 [Preliminary]
The PC8240’s features serve a variety of embedded applications. In this way, the 603e core and periph-
eral logic remain general-purpose. The PC8240 can be used as either a PCI host or an agent controller.
Screening/Quality/Packaging
This product is manufactured in full compliance with:
• Upscreening based upon e2v standards
• Industrial temperature range
(Tc = –40°C, Tc = +110° C)
(Tc = –40°C, Tc = +125° C): ZD3 suffix
• Core power supply:
2.5 ± 5 % V (L-Spec for 200 MHz)
• I/O power supply: 3.0V to 3.6V
• 352 Tape Ball Grid Array (TBGA)
TP suffix
TBGA352
Tape Ball Grid Array
2
0885C–HIREL–02/09
e2v semiconductors SAS 2009


Part Number PC8240
Description Integrated Processor
Maker e2v
Total Page 30 Pages
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