Datasheet Details
| Part number | 54AC11112 |
|---|---|
| Manufacturer | Texas Instruments |
| File Size | 105.34 KB |
| Description | DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS |
| Download | 54AC11112 Download (PDF) |
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| Part number | 54AC11112 |
|---|---|
| Manufacturer | Texas Instruments |
| File Size | 105.34 KB |
| Description | DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS |
| Download | 54AC11112 Download (PDF) |
|
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1CLK 1CLR NC V CC 2CLR These devices contain two independent J-K negative-edge-triggered flip-flops.
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of the other inputs.
When preset and clear are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock pulse.
54AC11112, 74AC11112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCAS073A – JUNE 1989 – REVISED APRIL 1993 • Flow-Through Architecture Optimizes PCB Layout • Center-Pin VCC and GND Configuration Minimizes High-Speed Switching Noise • EPIC ™ (Enhanced-Performance Implanted CMOS) 1-µm Process • 500-mA Typical Latch-Up Immunity at 125°C • ESD Protection Exceeds 2000 V, MIL STD-883C Method 3015 • Package Options Include Plastic Small- Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs 54AC11112 .
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| Part Number | Description |
|---|---|
| 54AC11109 | Dual J-K Positive-edge-Triggered Flip-Flops |
| 54AC11175 | QUADRUPLE D-TYPE FLIP-FLOPS |
| 54AC11002 | QUADRUPLE 2-INPUT POSITIVE-NOR GATES |
| 54AC11010 | TRIPLE 3-INPUT POSITIVE-NAND GATES |
| 54AC11011 | TRIPLE 3-INPUT POSITIVE-AND GATES |
| 54AC11021 | Dual 4-Input Positive-AND Gates |
| 54AC11027 | TRIPLE 3-INPUT POSITIVE-NOR GATES |
| 54AC11030 | 8-Input Positive-NAND Gates |
| 54AC11034 | HEX NONINVERTERS |
| 54AC11238 | 3-Line to 8-Line Decoders/Demultiplecers |